* Tero Kristo [151218 05:57]:
> This avoids the need to add most of the clock aliases under
> drivers/clk/ti/clk-xyz.c files.
Yup is badly needed. Right now we have strange hidden dependencies
in multiple subsystems to enable a single device driver:
1. Add a clock alias for a
The EMC clock sources for tegra210 currently incorrectly include pll_c2
and pll_c3. However, both of these should have been pll_mb as shown in
the TRM. If tegra210 happens to be configured such that the pll_mb is the
default clock for the EMC, as configured by the bootloader, then this will
cause
Replace the usage of prcm->clkstctrl with main_clk:s provided via DT.
This is done in preparation to get rid of hwmod data from kernel.
Signed-off-by: Tero Kristo
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 339
1 file changed, 95
The clock data in DT has been updated, and the clock aliases must be
updated to match.
Signed-off-by: Tero Kristo
---
drivers/clk/ti/clk-44xx.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/ti/clk-44xx.c
Clksel support has been deprecated a while back, so remove these from
the struct also.
Signed-off-by: Tero Kristo
---
include/linux/clk/ti.h |4
1 file changed, 4 deletions(-)
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 223be69..ec5613a 100644
get_parent and set_parent are going to be required by the support of
module clocks, so export these locally.
Signed-off-by: Tero Kristo
---
drivers/clk/ti/clock.h |3 +++
drivers/clk/ti/mux.c |4 ++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git
Previously, hwmod core has been used for controlling the hwmod level
clocks. This has certain drawbacks, like being unable to share the
clocks for multiple users, missing usecounting and generally being
totally incompatible with common clock framework.
Add support for new clock type under the TI
This avoids the need to add clock aliases under drivers/clk/ti/clk-xyz.c
files.
Signed-off-by: Tero Kristo
---
arch/arm/mach-omap2/omap_hwmod.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c
Hi,
This series adds support for hwmod gate clock type, and changes OMAP4
as an example to use the new clock type, converting the existing
hwmod_data clkctrl definitions to clock nodes under device tree.
Some additional magic is required for handling timer clocks, as the
clock driver assumes it
Document the new TI module clock type, which is intended to replace the
internal clock control handling within omap_hwmod. Module clock is
effectively a gate clock controlling both interface and functional
clocks for a single hardware IP block.
Signed-off-by: Tero Kristo
---
This avoids the need to add most of the clock aliases under
drivers/clk/ti/clk-xyz.c files.
Signed-off-by: Tero Kristo
---
arch/arm/mach-omap2/omap_device.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_device.c
* Tero Kristo [151218 05:57]:
> Previously, hwmod core has been used for controlling the hwmod level
> clocks. This has certain drawbacks, like being unable to share the
> clocks for multiple users, missing usecounting and generally being
> totally incompatible with common clock
* Tero Kristo [151218 05:57]:
> + mmu_dsp_mod_ck: mmu_dsp_mod_ck {
> + #clock-cells = <0>;
> + compatible = "ti,omap4-hw-mod-clock";
> + reg = <0x0420>;
> + clocks = <_iva_m4x2_ck>;
> + };
> +
> + dsp_mod_ck: dsp_mod_ck
On 12/18/2015 8:45 AM, Jon Hunter wrote:
> The EMC clock sources for tegra210 currently incorrectly include pll_c2
> and pll_c3. However, both of these should have been pll_mb as shown in
> the TRM. If tegra210 happens to be configured such that the pll_mb is the
> default clock for the EMC, as
Hi Stephen/Michael,
If these clock changes look fine to you, can they be merged for v4.5?
Thanks,
Ray
On 12/3/2015 9:37 AM, Ray Jui wrote:
Hi Stephen/Mike,
Do these clock changes look okay to you?
Thanks,
Ray
On 11/24/2015 4:13 PM, Florian Fainelli wrote:
On 23/11/15 09:50, Ray Jui
Heiko,
On Fri, Dec 18, 2015 at 10:33 AM, Heiko Stübner
wrote:
> As commit 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before
> reboot for rk3288") states, switching the PLLs to slow-mode is only
> necessary when rebooting using the soft-reset done through
On Tue, Dec 15, 2015 at 03:35:57PM -0800, Eric Anholt wrote:
> These will be used for enabling UART1, SPI1, and SPI2.
>
> Signed-off-by: Eric Anholt
> ---
>
> v2: Make the binding cover both the IRQ and clock enable registers.
>
> .../bindings/clock/brcm,bcm2835-aux-clock.txt
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