[PATCH 0/2] Bring up rk3399 ddr frequency scaling

these patchset bring up rk3399 ddr frequency scaling flow, use devfreq framework and simple_ondemand policy. Ddr set rate function will implement in dcf controller which run in the ATF, and rk3399 ATF not ready now, so we need finish it when rk3399 ATF ready. Lin Huang (2): clk: rockchip: dmc:

Re: [PATCH 1/2] clk: samsung: Don't build ARMv8 clock drivers on ARMv7

2015-11-19 13:51 GMT+09:00 Krzysztof Kozlowski : > On 19.11.2015 13:18, Tomasz Figa wrote: >> However, I don't think we can disable compilation of particular 64-bit >> SoCs, so maybe there isn't much sense in splitting their clock drivers >> into separate symbols? > > To

Re: [PATCH 1/2] clk: samsung: Don't build ARMv8 clock drivers on ARMv7

W dniu 19.11.2015 o 18:16, Tomasz Figa pisze: > 2015-11-19 13:51 GMT+09:00 Krzysztof Kozlowski : >> On 19.11.2015 13:18, Tomasz Figa wrote: >>> However, I don't think we can disable compilation of particular 64-bit >>> SoCs, so maybe there isn't much sense in splitting

[PATCH] clk: xgene: Fix divider with non-zero shift value

The X-Gene clock driver missed the divider shift operation when set the divider value. Signed-off-by: Loc Ho --- drivers/clk/clk-xgene.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c index

[PATCH 1/2] drivers: sh: clk: Avoid crashes when passing NULL clocks

Several clock API functions handle NULL clocks when the Common Clock Framework is used, while their legacy SH counterparts don't, and would just crash when a NULL clock is passed. Add NULL checks to clk_get_rate(), clk_set_rate(), clk_get_parent(), and clk_round_rate(), to avoid different

[PATCH 2/2] drivers: sh: clk: Remove obsolete and unused clk_round_parent()

clk_round_parent() was only ever used by AP4EVB, until commit b24bd7e97b3784af ("ARM: shmobile: Remove AP4EVB board support"). The Common Clock Framework does not provide clk_round_parent(), hence remove it. Signed-off-by: Geert Uytterhoeven --- drivers/sh/clk/core.c

Re: [PATCH 1/2] clk: mediatek: make dpi0_sel and hdmi_sel not propagate rate changes

+Heiko and +dianders who worked so hard to get the multi-stage HDMI clocks behaving well for the rk3288. On Thu, Nov 19, 2015 at 11:59 PM, Philipp Zabel wrote: > These muxes are supposed to select a fitting divider after the PLL > is already set to the correct rate. > >

Re: [PATCH 1/2] clk: rockchip: dmc: support rk3399 dmc clock driver

Hi Heiko, On 20/11/15 05:47, Heiko Stuebner wrote: Hi Lin, Am Donnerstag, 19. November 2015, 18:21:10 schrieb Lin Huang: support rk3399 dmc clock driver. Note, ddr set rate function will use dcf controller which run in ATF, it need to fishish it when rk3399 arm trust firmware ready. this

[PATCH v2 1/2] clk: samsung: Don't build ARMv8 clock drivers on ARMv7

Currently the Exynos5433 (ARMv8 SoC) clock driver depends on ARCH_EXYNOS so it is built also on ARMv7. This does not bring any kind of benefit. There won't be a single kernel image for ARMv7 and ARMv8 SoCs (like multi_v7 for ARMv7). Instead build clock drivers only for respective SoC's

[PATCH v2 2/2] arm64: EXYNOS: Consolidate ARCH_EXYNOS7 symbol into ARCH_EXYNOS

The ARMv8 Exynos family SoCs in Linux kernel are currently: - Exynos5433 (controlled by ARCH_EXYNOS), - Exynos7 (controlled by ARCH_EXYNOS7). It duplicates Kconfig symbols unnecessarily, so consolidate them into one ARCH_EXYNOS. Future SoCs could fall also under the ARCH_EXYNOS symbol. The

[PATCH v2 0/2] arm64: EXYNOS: Consolidate Exynos7 symbol

Hi, We don't need ARCH_EXYNOS7 symbol because all ARMv8 platforms should fall under generic ARCH_EXYNOS. In the same time there is no sense in building clocks for these ARMv8 SoCs on ARMv7 builds. In future this will also influence PMU [1] driver. Patch 2 *depends* on patch 1. Patch 1 received

Re: [PATCH v4 0/3] clk: Broadcom BCM63138 support

On 29/10/15 18:23, Florian Fainelli wrote: > This patch series adds support for the Broadcom BCM63138 DSL SoCs > clocking framework. > > Since the HW is identical to the one found in Broadcom iProc SoCs, but the > integration is different (obviously), there is still a new compatible string >

[PATCH 02/11] dt-bindings: clock: add description of LPC32xx USB clock controller

NXP LPC32xx USB controller has a subdevice, which controls USB AHB slave, USB OTG, USB OHCI, USB device and I2C controller to USB phy clocks, this change adds description of the clock controller, for more details reference LPC32xx User's Manual, namely USB control, OTG clock control and OTG clock

[PATCH 05/11] arm: dts: lpc32xx: add clock controller device node

NXP LPC32xx SoC has a clocking and power control unit (CPC) as a part of system control block (SCB). CPC is supplied by two external oscillators and it manages core and most of peripheral clocks, the change adds SCB and CPC descriptions to shared LPC32xx dtsi file. Signed-off-by: Vladimir

[PATCH 06/11] arm: dts: lpc32xx: add clock properties to device nodes

The change adds clock properties to all described peripheral devices, clock ids are taken from dt-bindings/clock/lpc32xx-clock.h Some existing drivers expect to get clock names, in those cases clock-names are added as well. Signed-off-by: Vladimir Zapolskiy ---

[PATCH 09/11] clk: lpc32xx: add common clock framework driver

Add support for all configurable clocks found on NXP LPC32xx SoC. The list contains several heterogenous groups of clocks: * system clocks including multiple dividers and muxes, * x397 PLL, HCLK PLL and USB PLL, * peripheral clocks inherited from rtc, hclk and pclk, * USB controller clocks: AHB

[PATCH 08/11] clk: lpc18xx: add NXP specific common clock framework selection

The change adds COMMON_CLK_NXP configuration symbol and enables it for NXP LPC18XX architecture, this is needed to reuse drivers/clk/nxp folder for NXP common clock framework drivers other than LPC18XX one. Signed-off-by: Vladimir Zapolskiy Cc: Joachim Eastwood

[PATCH 03/11] dt-bindings: clock: add NXP LPC32xx clock list for consumers

The change adds a list of NXP LPC32xx clocks, which can be requested by clock consumers. Signed-off-by: Vladimir Zapolskiy --- include/dt-bindings/clock/lpc32xx-clock.h | 56 +++ 1 file changed, 56 insertions(+) create mode 100644

[PATCH 11/11] arm: dts: lpc32xx: remove clock frequency property from UART device nodes

If clock-frequency property is given, then it substitutes calculation of supplying clock frequency from parent clock, this may break UART, if parent clock is given and managed by common clock framework. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 4

[PATCH 07/11] arm: dts: lpc32xx: add USB clock controller

The change adds device node of LPC32xx USB clock controller and adds clock properties to USB OHCI, USB device and I2C controller to USB phy device nodes. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 9 + 1 file changed, 9 insertions(+) diff

[PATCH 04/11] arm: dts: lpc32xx: add device nodes for external oscillators

NXP LPC32xx SoC has two external oscillators - one is mandatory and always on 32768 Hz oscillator and one optional 10-20MHz oscillator, which is practically always present on LPC32xx boards, because its presence is needed to supply USB controller clock and by default it supplies ARM and most of

Re: [PATCH v4 0/3] clk: Broadcom BCM63138 support

On 19/11/15 17:00, Florian Fainelli wrote: > On 29/10/15 18:23, Florian Fainelli wrote: >> This patch series adds support for the Broadcom BCM63138 DSL SoCs >> clocking framework. >> >> Since the HW is identical to the one found in Broadcom iProc SoCs, but the >> integration is different

Re: [PATCH] clk: si5351: Add setup steps

On 19.11.2015 14:40, Jacob Siverskog wrote: > This is according to figure 12 ("I2C Programming Procedure") in > "Si5351A/B/C Data Sheet" > (https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf). > > Without the PLL soft reset, we were unable to get three outputs > working at the

Re: [PATCH 1/2] clk: rockchip: dmc: support rk3399 dmc clock driver

Hi Lin, Am Donnerstag, 19. November 2015, 18:21:10 schrieb Lin Huang: > support rk3399 dmc clock driver. Note, ddr set rate function will > use dcf controller which run in ATF, it need to fishish it when rk3399 > arm trust firmware ready. this unfinalized state is slightly unfortunate and I

[PATCH v3 2/6] clk: qcom: Add IPQ4019 Global Clock Controller support

From: Varadarajan Narayanan This patch adds support for the global clock controller found on the IPQ4019 based devices. This includes UART, I2C, SPI etc. Signed-off-by: Pradeep Banavathi Signed-off-by: Senthilkumar N L

[PATCH] clk: tegra: move _calc_dynamic_ram_rate out of #ifdef

_calc_dynamic_ram_rate is defined inside an #ifdef but called later in the same file outside of that #ifdef, which can cause a build error: drivers/clk/tegra/clk-pll.c: In function '_tegra_clk_register_pll': drivers/clk/tegra/clk-pll.c:1541:29: error: '_calc_dynamic_ramp_rate' undeclared (first

Re: [PATCH 1/2] clk: samsung: Don't build ARMv8 clock drivers on ARMv7

On 19/11/15 10:16, Tomasz Figa wrote: > 2015-11-19 13:51 GMT+09:00 Krzysztof Kozlowski : >> > On 19.11.2015 13:18, Tomasz Figa wrote: >>> >> However, I don't think we can disable compilation of particular >>> >> 64-bit SoCs, so maybe there isn't much sense in splitting

[PATCH] clk: use IS_ERR_OR_NULL(hw) instead of !hw || IS_ERR(hw)

This minor refactoring does not change the function behavior. Signed-off-by: Masahiro Yamada --- drivers/clk/clk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index f13c3f4..764aca2 100644 ---

Re: [PATCH v3 00/12] Add mipi dsi support for rk3288

Hi Emil On 11/19/2015 10:41 PM, Emil Velikov wrote: On 19 November 2015 at 03:35, Chris Zhong wrote: The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP. This series adds support for a Synopsys DesignWare MIPI DSI host controller DRM bridge driver and

[PATCH 3/3] clk: split of_clk_get_parent_name() into two functions

Currently, there is no function to get the clock name of the given node. Create a new helper function, of_clk_get_name(). This is useful to get the clock name where "clock-indices" property is used. of_clk_get_name(): get the clock name in the given node of_clk_get_parent_name(): get the

[PATCH 2/3] clk: let of_clk_get_parent_name() fail for invalid clock-indices

Currently, of_clk_get_parent_name() returns a wrong parent clock name when "clock-indices" property exists and the given index is not found in the property. In this case, NULL should be returned. For example, oscillator { compatible = "myclocktype";

[PATCH 1/3] clk: remove redundant negative index check in of_clk_get_parent_name()

This if-block can be dropped because the of_parse_phandle_with_args() in the following line returns -EINVAL for negative index. Signed-off-by: Masahiro Yamada --- drivers/clk/clk.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/clk/clk.c

Re: [PATCH] scpi: hide get_scpi_ops in module from built-in code

On Tuesday 17 November 2015 17:30:14 Punit Agrawal wrote: > Arnd Bergmann writes: > > > The scpi_clock driver can be built-in when CONFIG_COMPILE_TEST > > is set even when ARM_SCPI_PROTOCOL is a loadable module, and > > that results in a link error: > > > > drivers/built-in.o: In

Re: [PATCH 05/19] clk: sunxi: add DRAM gates

On Fri, Nov 13, 2015 at 04:08:53PM +0800, Chen-Yu Tsai wrote: > On Mon, Nov 9, 2015 at 12:18 PM, Chen-Yu Tsai wrote: > > On Fri, Oct 30, 2015 at 10:20 PM, Maxime Ripard > > wrote: > >> The Allwinner SoCs have a gate controller to gate the access

[PATCH 2/2] clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output

The configurable hdmi_ref output of the PLL block is derived from the tvdpll_594m clock signal via a configurable PLL post-divider. It is used as the PLL reference input to the HDMI PHY module. Signed-off-by: Philipp Zabel --- drivers/clk/mediatek/clk-mt8173.c | 5

Re: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock

On Mon, Nov 09, 2015 at 11:36:15AM +0800, Chen-Yu Tsai wrote: > >> > + sclk1_parents[0] = sclk2_name; > >> > + sclk1_parents[1] = sclk2d2_name; > >> > >> Is there any need to expose these 2 clocks via DT using > >> of_clk_add_provider? > > > > No, as far as I'm aware, there's no user

Re: [PATCH 01/19] clk: sunxi: Add display clock

On Thu, Nov 12, 2015 at 12:31:54PM -0800, Stephen Boyd wrote: > On 11/06, Maxime Ripard wrote: > > Hi Stephen, > > > > Thanks for your feedback! > > > > On Fri, Oct 30, 2015 at 02:29:02PM -0700, Stephen Boyd wrote: > > > > + > > > > + mux = kzalloc(sizeof(*mux), GFP_KERNEL); > > > > +

[PATCH 0/2] MT8173 clock changes for DRM

Hi, I have sent these two as part of the MT8173 DRM/KMS driver patch series [1], but not yet to the clock list. I'd be happy to get some review and suggestions on how to best merge them, given the dependency of the DRM/KMS driver on these changes. [1]

[PATCH v4 4/5] clk: qcom: Add RPM clock controller driver

Add support for clocks that are controlled by the RPM processor on Qualcomm msm8916 based platforms. Signed-off-by: Georgi Djakov --- .../devicetree/bindings/clock/qcom,rpmcc.txt | 35 drivers/clk/qcom/Kconfig |8 +

[PATCH v4 0/5] Add initial support for RPM clocks

This patchset adds initial support for the clocks controlled by the RPM (Resource Power Manager) processor on Qualcomm platforms. The RPM is a dedicated hardware engine for managing the shared SoC resources in order to keep the lowest power profile. It communicates with other hardware subsystems

Re: [PATCH] thermal: Add support for Sunxi THS on the Allwinner H3

On Wed, Nov 18, 2015 at 09:51:48PM +0100, Josef Gajdusek wrote: > This patch adds support for the Sunxi thermal sensor on the Allwinner H3. > Also adds declaration of the H3 THS clock to clk-sunxi.c ignoring the > dividers as they are not continuous (clk-divider.c cannot be used as it > does not

[PATCH v4 3/5] clk: qcom: Add support for RPM Clocks

This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor found on some Qualcomm SoCs. The RPM is a dedicated hardware engine for managing the shared SoC resources in order to keep the lowest power profile. It communicates with other hardware subsystems via

[PATCH v4 5/5] arm64: dts: qcom: msm8916: Add RPMCC DT node

Add the RPM Clock Controller DT node and include the necessary header file for clocks. Signed-off-by: Georgi Djakov --- arch/arm64/boot/dts/qcom/msm8916.dtsi |6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi

[PATCH v4 2/5] arm64: dts: qcom: msm8916: Add fixed rate on-board oscillator

Currently the rates of the xo and sleep clocks are hard-coded in the GCC driver, but this is a board layout description that actually should be in the DT. Moving them into DT also allows us to insert the RPM controlled clocks between the DT and GCC clocks. Signed-off-by: Georgi Djakov

[PATCH v4 1/5] clk: qcom: msm8916: Move xo and sleep clocks into DT

Move the xo and sleep clocks to device-tree, instead of hard-coding them in the driver. This allows us to insert the RPM clocks (if they are enabled) in between the on-board oscillators and the actual clock. Signed-off-by: Georgi Djakov ---

imx6dl clock setup incorrectness

Hi While working with board with imx6s cpu, with kernel based on linux-imx imx_3.14.28_1.0.0_ga branch, I noticed this message in boot log: > failed to set parent of clk gpu2d_core_sel to pll2_pfd1_594m I looked into it and found that: - CCM_CBCMR register layout is different between

Re: [PATCH v3 00/12] Add mipi dsi support for rk3288

On 19 November 2015 at 03:35, Chris Zhong wrote: > The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller > IP. This series adds support for a Synopsys DesignWare MIPI DSI host > controller DRM bridge driver and a rockchip MIPI DSI specific DRM > driver. > >