Re: [PATCH 1/3] dt-bindings: add Marvell core PLL and clock divider PMU documentation

On Fri, Nov 27, 2015 at 08:39:32PM +, Russell King - ARM Linux wrote: > On Fri, Nov 27, 2015 at 02:21:14PM -0600, Rob Herring wrote: > > On Thu, Nov 26, 2015 at 10:23:21PM +, Russell King wrote: > > > Add documentation for the Marvell clock divider driver, which is used > > > to source

[PATCH v3] clk: s3c2410: removed unneeded variable in s3c24xx_clkout_set_parent

From: Prasanna Karthik Remove unneeded variable used to store return value. Signed-off-by: Prasanna Karthik --- v3: Modified subject and changelog comments --- --- drivers/clk/samsung/clk-s3c2410-dclk.c | 3 +-- 1 file changed, 1 insertion(+), 2

Re: [PATCH v3] clk: s3c2410: removed unneeded variable in s3c24xx_clkout_set_parent

2015-11-30 19:08 GMT+09:00 Mutharaju, Prasanna (P.) : > From: Prasanna Karthik > > Remove unneeded variable used to store return value. > > Signed-off-by: Prasanna Karthik Thanks, Reviewed-by: Krzysztof Kozlowski

[PATCH 2/2] clk: axi-clkgen: Add multi-parent support

The clock generator has two clock inputs that can be used as the reference clock. Add support for switching between them at runtime. Signed-off-by: Lars-Peter Clausen --- .../devicetree/bindings/clock/axi-clkgen.txt | 5 ++- drivers/clk/clk-axi-clkgen.c

[PATCH 1/2] clk: axi-clkgen: Remove version 1 support

Version 1 of the axi-clkgen core has not been used in new designs for over two years now. This is a soft peripheral used in FPGAs and anybody who has updated their kernel to the latest version will also have updated the bitstream containing the clock generator. So it should be safe to drop support

Re: [PATCH v4 3/5] clk: sunxi: Add sun9i A80 cpus (cpu special) clock support

On Sun, Nov 29, 2015 at 11:03:08AM +0800, Chen-Yu Tsai wrote: > The "cpus" clock is the clock for the embedded processor in the A80. > It is also part of the PRCM clock tree. This clock includes a pre- > divider on one of its inputs. For now we are using a custom clock > driver for it. In the

Re: [PATCH v4 2/5] clk: sunxi: Add sun9i A80 apbs gates support

On Sun, Nov 29, 2015 at 11:03:07AM +0800, Chen-Yu Tsai wrote: > This patch adds support for the PRCM apbs clock gates found on the > Allwinner A80 SoC. > > Signed-off-by: Chen-Yu Tsai Acked-by: Rob Herring > --- >

[PATCH] clk: sunxi: pll2: Fix clock running too fast

Contrary to what the datasheet says, the pre divider doesn't seem to be incremented by one in the PLL2, but just uses the value from the register, with 0 being a bypass. This fixes the audio playing too fast. Since we now have the same pre-divider flags, and the only difference with the A10 is

Re: [PATCH] clk: sunxi: pll2: Fix clock running too fast

On 11/30, Maxime Ripard wrote: > @@ -191,25 +186,17 @@ err_unmap: > iounmap(reg); > } > > -static struct sun4i_pll2_data sun4i_a10_pll2_data = { > - .pre_div_flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, > -}; > - > static void __init sun4i_a10_pll2_setup(struct

Re: [PATCH] clk: sunxi: pll2: Fix clock running too fast

On 11/30, Maxime Ripard wrote: > Contrary to what the datasheet says, the pre divider doesn't seem to be > incremented by one in the PLL2, but just uses the value from the register, > with 0 being a bypass. > > This fixes the audio playing too fast. > > Since we now have the same pre-divider

Re: [PATCH] clk: fix a typo in comment block of clk_notifier_register()

On 11/30, Masahiro Yamada wrote: > The word "cases" is doubled. Keep decent forms for the following > lines. > > Signed-off-by: Masahiro Yamada > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation

Re: [PATCH] clk: ti: omap5+: dpll: implement errata i810

On 11/30, Tero Kristo wrote: > Errata i810 states that DPLL controller can get stuck while transitioning > to a power saving state, while its M/N ratio is being re-programmed. > > As a workaround, before re-programming the M/N ratio, SW has to ensure > the DPLL cannot start an idle state

Re: [PATCH] clk: sunxi: pll2: Fix clock running too fast

Hi Maxime, [auto build test ERROR on: clk/clk-next] [also build test ERROR on: v4.4-rc3 next-20151127] url: https://github.com/0day-ci/linux/commits/Maxime-Ripard/clk-sunxi-pll2-Fix-clock-running-too-fast/20151130-233840 base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git

Re: [PATCH] clk: sunxi: pll2: Fix clock running too fast

On Mon, Nov 30, 2015 at 11:32:16AM -0800, Stephen Boyd wrote: > On 11/30, Maxime Ripard wrote: > > @@ -191,25 +186,17 @@ err_unmap: > > iounmap(reg); > > } > > > > -static struct sun4i_pll2_data sun4i_a10_pll2_data = { > > - .pre_div_flags = CLK_DIVIDER_ONE_BASED |

Re: [PATCH 1/5] clk: hi3519: add CRG driver for hisilicon hi3519 soc

On Sat, Nov 28, 2015 at 03:13:26PM +0800, Jiancheng Xue wrote: > The CRG(Clock and Reset Generator) module provides > clock and reset signals for other modules in hi3519 soc. > > Signed-off-by: Jiancheng Xue > --- > .../devicetree/bindings/clock/hi3519-clock.txt |

Re: [PATCH 1/3] ARM: imx: clk-vf610: fix SAI clock tree

On 11/23, Shawn Guo wrote: > On Sat, Oct 17, 2015 at 09:05:20PM -0700, Stefan Agner wrote: > > > > Since Patch 3 also uses the fixed clock layout, it should be > > applied after the clock tree fix too... > > > > Not sure through which tree these changes should go? > > Mike, Stephen, > > Can I

Re: [PATCH] imx/clk-pllv2: fix wrong do_div() usage

On 11/03, Nicolas Pitre wrote: > do_div() is meant to be used with an unsigned dividend. > > Signed-off-by: Nicolas Pitre > Applied to clk-fixes -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe

Re: [PATCH] imx/clk-pllv1: fix wrong do_div() usage

On 11/03, Nicolas Pitre wrote: > do_div() is meant to be used with an unsigned dividend. > > Signed-off-by: Nicolas Pitre > Applied to clk-fixes -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe

[PATCH 1/2] clk: Add brcm,bcm63xx-gate-clk device tree binding

Add device tree binding for the BCM63xx's gated clocks. The BCM63xx contains clocks gated with a register. Clocks are indexed by bits in the register and are active high. Clock gate bits are interleaved with other status bits and configurable clocks in the same register. Signed-off-by: Simon

[PATCH 2/2] clk: bcm63xx: Add BCM63xx gated clock support

The BCM63xx contains clocks gated with a register. Clocks are indexed by bits in the register and are active high. Clock gate bits are interleaved with other status bits and configurable clocks in the same register. Enabled by default for BMIPS_GENERIC. Signed-off-by: Simon Arlott

Re: [PATCH 5/6] clk: qcom: gdsc: Do not check for disabled status on votable gdscs

On 11/26, Rajendra Nayak wrote: > Some gdscs might be controlled via voting registers and might not > really disable when the kernel intends to disable them (due to other > votes keeping them enabled) > Mark these gdscs with a flag for we do not check/wait on a disable > status for these gdscs

Re: [PATCH v2] clk: let of_clk_get_parent_name() fail for invalid clock-indices

On 11/30, Masahiro Yamada wrote: > Currently, of_clk_get_parent_name() returns a wrong parent clock name > when "clock-indices" property exists and the target index is not > found in the property. In this case, NULL should be returned. > > For example, > > oscillator { >

[PATCH v2 0/5] Add support for MSM8996 clock controllers

These patches add support for the global and multimedia clock controllers found on MSM8996 devices. The first patch allows us to implement a "power of two" divider of different widths with a table based divider. The second patch adds support for Alpha PLLs and the 3rd and 5th patches add support

[PATCH v2 5/5] clk: qcom: Add MSM8996 Multimedia Clock Controller (MMCC) driver

Add a driver for the multimedia clock controller found on MSM8996 based devices. This should allow most multimedia device drivers to probe and control their clocks. Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/qcom,mmcc.txt|1 +

[PATCH v2 1/5] clk: divider: Cap table divider values to 'width' member

When we use a clk divider with a divider table, we limit the maximum divider value in divider_get_val() to the div_mask(width), but when we calculate the divider in divider_round_rate() we don't consider that the maximum divider may be limited by the width. Pass the width along to

[PATCH v2 4/5] clk: qcom: Add gfx3d ping-pong PLL frequency switching

The GPU clocks on msm8996 have three dedicated PLLs, MMPLL2, MMPLL8, and MMPLL9. We leave MMPLL9 at the maximum speed (624 MHz), and we use MMPLL2 and MMPLL8 for the other frequencies. To make switching frequencies faster, we ping-pong between MMPLL2 and MMPLL8 when we're switching between

Re: [PATCH 2/6] clk: qcom: gdsc: Add support for gdscs with gds hw controller

On 11/26, Rajendra Nayak wrote: > @@ -58,30 +58,34 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en) > { > int ret; > u32 val = en ? 0 : SW_COLLAPSE_MASK; > - u32 check = en ? PWR_ON_MASK : 0; > unsigned long timeout; > + unsigned int status_reg = sc->gdscr; >

Re: [PATCH v2 0/5] Add support for MSM8996 clock controllers

On 11/30, Stephen Boyd wrote: > These patches add support for the global and multimedia clock controllers > found on MSM8996 devices. The first patch allows us to implement a > "power of two" divider of different widths with a table based divider. > The second patch adds support for Alpha PLLs and

Re: [PATCH 1/5] clk: hi3519: add CRG driver for hisilicon hi3519 soc

Hello Rob, Thanks for your suggestions! On 2015/12/1 4:35, Rob Herring wrote: > On Sat, Nov 28, 2015 at 03:13:26PM +0800, Jiancheng Xue wrote: >> The CRG(Clock and Reset Generator) module provides >> clock and reset signals for other modules in hi3519 soc. >> >> Signed-off-by: Jiancheng Xue

Re: [PATCH v2] clk: let of_clk_get_parent_name() fail for invalid clock-indices

Hi Stephen, 2015-12-01 9:58 GMT+09:00 Stephen Boyd : > On 11/30, Masahiro Yamada wrote: >> Currently, of_clk_get_parent_name() returns a wrong parent clock name >> when "clock-indices" property exists and the target index is not >> found in the property. In this case, NULL

Re: [PATCH 5/6] clk: qcom: gdsc: Do not check for disabled status on votable gdscs

On 12/01/2015 07:23 AM, Stephen Boyd wrote: > On 11/26, Rajendra Nayak wrote: >> Some gdscs might be controlled via voting registers and might not >> really disable when the kernel intends to disable them (due to other >> votes keeping them enabled) >> Mark these gdscs with a flag for we do not

Re: [PATCH 3/3] clk: split of_clk_get_parent_name() into two functions

2015-12-01 9:49 GMT+09:00 Stephen Boyd : > On 11/24, Masahiro Yamada wrote: >> Hi Stephen, >> >> >> 2015-11-22 14:44 GMT+09:00 Masahiro Yamada : >> > Hi Stephen, >> > >> > >> > 2015-11-21 9:37 GMT+09:00 Stephen Boyd : >> >>

Re: [PATCH 2/6] clk: qcom: gdsc: Add support for gdscs with gds hw controller

On 12/01/2015 07:52 AM, Stephen Boyd wrote: > On 11/26, Rajendra Nayak wrote: >> @@ -58,30 +58,34 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en) >> { >> int ret; >> u32 val = en ? 0 : SW_COLLAPSE_MASK; >> -u32 check = en ? PWR_ON_MASK : 0; >> unsigned long timeout;

Re: [PATCH 5/5] clk: scpi: add missing of_node_put

On 11/26, Sudeep Holla wrote: > Hi Mike/Stephen, > > On Thu, Oct 22, 2015 at 10:21 AM, Sudeep Holla wrote: > > > > > > Thanks for the fix. > > > > Acked-by: Sudeep Holla > > > > PS: Since this driver is queued via arm-soc, it needs to go via them or >

Re: [PATCH 5/5] clk: scpi: add missing of_node_put

On 10/21, Julia Lawall wrote: > for_each_available_child_of_node performs an of_node_get on each iteration, > so a break out of the loop requires an of_node_put. > > The semantic patch that fixes this problem is as follows > (http://coccinelle.lip6.fr): > > // > @@ > expression root,e; > local

Re: [PATCH 2/3] clk: let of_clk_get_parent_name() fail for invalid clock-indices

On 11/30, Masahiro Yamada wrote: > Hi Stephen, > > > > >> > >> Of course we can, although we have to mention "clock-indices" twice. > >> > >> A good thing for of_get_property() is that we can get both the value > >> and the length > >> at the same time. > >> > > > > Ok. Well if we don't want to

Re: [PATCH] clk: imx: Replace clk error check with imx_check_clocks()

On 11/26, Bai Ping wrote: > As we already have a 'imx_check_clocks' to do the clock error > check, so cleanup the error check code. > > Signed-off-by: Bai Ping > --- Acked-by: Stephen Boyd -- Qualcomm Innovation Center, Inc. is a member of Code

Re: [PATCH v6] clk: add CS2000 Fractional-N driver

On 11/10, Kuninori Morimoto wrote: > From: Kuninori Morimoto > > This patch adds CS2000 Fractional-N driver as clock provider. > > Signed-off-by: Kuninori Morimoto > --- Applied to clk-next -- Qualcomm Innovation Center,

Re: [PATCH 3/3] clk: split of_clk_get_parent_name() into two functions

On 11/24, Masahiro Yamada wrote: > Hi Stephen, > > > 2015-11-22 14:44 GMT+09:00 Masahiro Yamada : > > Hi Stephen, > > > > > > 2015-11-21 9:37 GMT+09:00 Stephen Boyd : > >> On 11/20, Masahiro Yamada wrote: > >>> Currently, there is no function

Re: [PATCH 2/6] clk: qcom: gdsc: Add support for gdscs with gds hw controller

On 12/01, Rajendra Nayak wrote: > > On 12/01/2015 07:52 AM, Stephen Boyd wrote: > > On 11/26, Rajendra Nayak wrote: > > > >> + udelay(1); > >> + } > >> + > >> + do { > >> + if (gdsc_is_enabled(sc, status_reg) == en) > >>return 0; > >>} while

Re: [PATCH v2] clk: s3c2410: removed unneeded variable in s3c24xx_clkout_set_parent

On Mon, Nov 30, 2015 at 04:31:35PM +0900, Krzysztof Kozlowski wrote: > On 30.11.2015 16:28, Mutharaju, Prasanna (P.) wrote: > > From: Prasanna Karthik > > > > Remove unneeded variable used to store return value. > > V2: Modified subject > > Changelog (v2) should go after

Re: [PATCH 2/3] clk: let of_clk_get_parent_name() fail for invalid clock-indices

Hi Stephen, >> >> Of course we can, although we have to mention "clock-indices" twice. >> >> A good thing for of_get_property() is that we can get both the value >> and the length >> at the same time. >> > > Ok. Well if we don't want to count them again, perhaps a goto > jump over an

[PATCH v2] clk: let of_clk_get_parent_name() fail for invalid clock-indices

Currently, of_clk_get_parent_name() returns a wrong parent clock name when "clock-indices" property exists and the target index is not found in the property. In this case, NULL should be returned. For example, oscillator { compatible = "myclocktype";

[PATCH] clk: ti: omap5+: dpll: implement errata i810

Errata i810 states that DPLL controller can get stuck while transitioning to a power saving state, while its M/N ratio is being re-programmed. As a workaround, before re-programming the M/N ratio, SW has to ensure the DPLL cannot start an idle state transition. SW can disable DPLL idling by