The rk3036's pll and clock are different with base on the rk3066(rk3188,
rk3288, rk3368 use it), there are different adjust foctors and control
registers, so these should be independent and separate from the series
of rk3066s.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Re
tion of rk3036 clock controller
Changes in v5:
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
Heiko Stuebner (1):
ARM: rockchip: add support smp for rk3036
Xing Zheng (7):
dt-bindings: add documentation of rk3036 clock controller
The rk3036's pll and clock are different with base on the rk3066(rk3188,
rk3288, rk3368 use it), there are different adjust foctors and control
registers, so these should be independent and separate from the series
of rk3066s.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Re
) ARM: dts: rockchip: add core rk3036 dts
4) clk: rockchip: add new pll-type for rk3036 and similar socs
3) clk: rockchip: add clock controller for rk3036
2) clk: rockchip: add dt-binding header for rk3036
1) dt-bindings: add documentation of rk3036 clock controller
Changes in v4:
Signed-off-by
Add the clock tree definition for the new rk3036 SoC.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v7: None
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk-rk3
for rk3036
3) clk: rockchip: add new pll-type for rk3036 and similar socs
2) clk: rockchip: add dt-binding header for rk3036
1) dt-bindings: add documentation of rk3036 clock controller
Changes in v7:
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he.
The rk3036's pll and clock are different with base on the rk3066(rk3188,
rk3288, rk3368 use it), there are different adjust foctors and control
registers, so these should be independent and separate from the series
of rk3066s.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Re
similar socs
2) clk: rockchip: add dt-binding header for rk3036
1) dt-bindings: add documentation of rk3036 clock controller
Changes in v6:
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Heiko Stuebner <he...@sntech.de>
Heiko Stuebner (1):
ARM: rockchip: add support smp
The rk3036's pll and clock are different with base on the rk3066(rk3188,
rk3288, rk3368 use it), there are different adjust foctors and control
registers, so these should be independent and separate from the series
of rk3066s.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Re
type :-) .
Xing Zheng now also independently stumbled upon this issue with his rk3036
work. And came to the same conclusion that the gate must be enabled as well as
the downstream mux be set to the fractional divider for it to actually accept
a new setting.
Yes, I discussed such problems with Heiko
Add the clock tree definition for the new rk3036 SoC.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---
Changes in v2: None
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk-rk3036.c | 504 +
drivers/clk/rockchip
controller for rk3036
2) clk: rockchip: add dt-binding header for rk3036
1) ARM: dts: rockchip: add core rk3036 dts
Changes in v2:
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Xing Zheng (9):
ARM: dts: rockchip: add core rk3036 dts
clk: rockchip: add dt-binding header for rk3036
On 2015年08月28日 17:54, Heiko Stuebner wrote:
Hi,
Am Freitag, 28. August 2015, 13:46:48 schrieb Xing Zheng:
Add the clock tree definition for the new rk3036 SoC,
but there are some issues to be fixed:
1. soc will crash if gpll run rate_change_remuxed
2. rk3036_clk_suspend and rk3036_clk_resume
The rk3036's pll and clock are different with base on the rk3066(rk3188,
rk3288, rk3368 use it), there are different adjust foctors and control
registers, so these should be independent and separate from the series
of rk3066s.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---
C
The rk3036's pll and clock are different with base on the rk3066(rk3188,
rk3288, rk3368 use it), there are different adjust foctors and control
registers, so these should be independent and separate from the series
of rk3066s.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Re
Hi:
In the development work, we found that some of the previous
incorrect clock configuration on the RK3036 platform, we should
fix them.
Xing Zheng (5):
clk: rockchip: rk3036: fix the FLAGs for clock mux
clk: rockchip: rk3036: fix uarts clock error
clk: rockchip: rk3036: fix the div
We need to add HCLK_MAC id explicitly because that it is referred
by hclk in the emac driver.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3036.c |2 +-
include/dt-bindings/clock/rk3036-cru.h |1 +
2 files changed, 2 insertions(+), 1 de
Due to a copy-paste error the uart1 and uart2 clock div set
incorrect, we should to fix it.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3036.c |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk
Hi:
In the development work, we found that some of the previous incorrect
clock configuration on the RK3036 platform, we should fix them.
Xing Zheng (4):
clk: rockchip: rk3036: fix the FLAGs for clock mux
clk: rockchip: rk3036: fix uarts clock error
clk: rockchip: rk3036: rename emac
There is only support rmii in the RK3036, so we should use the correct
ext clock name.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3036.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3036.c
b/d
The DFLAGS are used for the clock dividers, the CLKSEL_CON flags
of COMPOSITE_NODIV type should be MFLAGS.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3036.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drive
There is only support rmii in the RK3036, so we should use the correct
ext clock name.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3036.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3036.c
b/d
the accurate rate for mac_ref which
need to 50MHz probability, we should let it under the APLL and are
able to set the freq which integer multiples of 50MHz, so we add these
emac node for reference.
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---
drivers/clk/rockchip/clk-rk
OK, Thanks Heiko. :-)
On 2015年11月24日 08:03, Heiko Stübner wrote:
Hi Xing Zheng,
Am Donnerstag, 5. November 2015, 15:33:54 schrieb Xing Zheng:
Hi,
We need to support rk3036 soc platform via upstream, there are
some primary parts for the initial release of minimum system: dts,
clk-pll, smp
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