On Mon, Dec 15, 2008 at 11:38:01PM +1100, Herbert Xu wrote:
On Mon, Dec 15, 2008 at 04:21:06PM +1100, Herbert Xu wrote:
a. Do not touch SSE state in soft_irq
b. Disable/restore soft_irq in kernel_fpu_begin/kernel_fpu_end
c. Use a per-CPU data structure to save kernel FPU state during
Huang Ying ying.hu...@intel.com wrote:
f. if TS is clear, then use x86_64 implementation. Otherwise if
user-space has touched the FPU, we save the state, if not then simply
clear TS.
Well I'd rather avoid using the x86_64 implementation ever because
unless the chip guys have really screwed up
On Wed, 2008-12-17 at 09:26 +0800, Herbert Xu wrote:
Huang Ying ying.hu...@intel.com wrote:
f. if TS is clear, then use x86_64 implementation. Otherwise if
user-space has touched the FPU, we save the state, if not then simply
clear TS.
Well I'd rather avoid using the x86_64
On Sun, Dec 07, 2008 at 11:17:27PM +0100, Adrian-Ken Rueegsegger wrote:
This resend contains the fixed up sha512 patches to switch the last
remaining algorithm to shash.
The first patch is now correct also in the case of preemption. The
second patch remains unchanged.
Both applied. Thanks
