Hi,
On Mon, Jun 9, 2014 at 6:59 PM, LABBE Corentin
clabbe.montj...@gmail.com wrote:
Add support for the Security System included in Allwinner SoC A20.
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
Signed-off-by: LABBE
On 9 June 2014 19:41, chandramouli narayanan mo...@linux.intel.com wrote:
[...]
@@ -1493,6 +1521,14 @@ static int __init aesni_init(void)
aesni_gcm_enc_tfm = aesni_gcm_enc;
aesni_gcm_dec_tfm = aesni_gcm_dec;
}
+ aesni_ctr_enc_tfm = aesni_ctr_enc;
On 06/10/14 08:53, Chen-Yu Tsai wrote:
Hi,
On Mon, Jun 9, 2014 at 6:59 PM, LABBE Corentin
clabbe.montj...@gmail.com wrote:
Add support for the Security System included in Allwinner SoC A20.
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG
Hi Joe,
On 06/09/2014 07:46 PM, Joe Perches wrote:
On Mon, 2014-06-09 at 15:08 +0300, Stanimir Varbanov wrote:
The driver is separated by functional parts. The core part
implements a platform driver probe and remove callbaks.
The probe enables clocks, checks crypto version, initialize
and
This patch adds documentation for Device-Tree bindings for the Security
System cryptographic accelerator driver.
Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com
---
Documentation/devicetree/bindings/crypto/sunxi-ss.txt | 9 +
1 file changed, 9 insertions(+)
create mode 100644
Hello
This is the driver for the Security System included in Allwinner SoC A20.
The Security System (SS for short) is a hardware cryptographic accelerator that
support AES/MD5/SHA1/DES/3DES/PRNG algorithms.
It could be found on others Allwinner SoC:
- A10s and A31 diagram speak about it with
Add support for the Security System included in Allwinner SoC A20.
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com
---
drivers/crypto/sunxi-ss/Makefile | 19 ++
Add necessary changes for configuring and compiling the Security System driver.
Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com
---
drivers/crypto/Kconfig | 91 +
drivers/crypto/Makefile | 1 +
2 files changed, 92 insertions(+)
diff
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
It could be found on many Allwinner SoC.
This patch enable the Security System on the Allwinner A20 SoC Device-tree.
Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com
---
This patch introduces by8 AES CTR mode AVX optimization inspired by
Intel Optimized IPSEC Cryptograhpic library. For additional information,
please see:
http://downloadcenter.intel.com/Detail_Desc.aspx?agr=YDwnldID=22972
The functions aes_ctr_enc_128_avx_by8(), aes_ctr_enc_192_avx_by8() and
On 10 June 2014 18:22, chandramouli narayanan mo...@linux.intel.com wrote:
This patch introduces by8 AES CTR mode AVX optimization inspired by
Intel Optimized IPSEC Cryptograhpic library. For additional information,
please see:
Hi Kim,
I contacted the Hardware folks and below is the statement from them :
Unfortunately setting the DWT bit will also affect the operation of
job descriptors, so I don't think that is a viable option. It looks
like you will have to change the software to access all 32-bit
registers as
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