Hi Herbert,
would you please merge this driver or is there anything else you want
me to address first?
Regards.
On 1 March 2013 12:37, Javier Martin javier.mar...@vista-silicon.com wrote:
SAHARA2 HW module is included in the i.MX27 SoC from
Freescale. It is capable of performing cipher
accelerator.
Regards.
--
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com
--
To unsubscribe from this list: send the line unsubscribe linux-crypto in
the body of a message to majord
Hi Sascha,
On 4 March 2013 08:53, Sascha Hauer s.ha...@pengutronix.de wrote:
On Fri, Mar 01, 2013 at 12:37:52PM +0100, Javier Martin wrote:
Signed-off-by: Javier Martin javier.mar...@vista-silicon.com
---
arch/arm/mach-imx/clk-imx27.c |2 ++
1 file changed, 2 insertions(+)
diff --git
Hi,
the following changes since v2:
- Merge device tree binding with the driver code in the same patch.
- Specify that currently, only i.MX27 is supported in device tree binding.
- Replace MACH_MX27 by ARCH_MXC in Kconfig.
- Remove __devexit_p from sahara_remove().
I haven't finally included
SAHARA2 HW module is included in the i.MX27 SoC from
Freescale. It is capable of performing cipher algorithms
such as AES, 3DES..., hashing and RNG too.
This driver provides support for AES-CBC and AES-ECB
by now.
Reviewed-by: Arnd Bergmann a...@arndb.de
Signed-off-by: Javier Martin javier.mar
Hi Arnaud,
On 28 February 2013 12:07, Arnaud Patard arnaud.pat...@rtp-net.org wrote:
Javier Martin javier.mar...@vista-silicon.com writes:
Hi,
SAHARA2 HW module is included in the i.MX27 SoC from
Freescale. It is capable of performing cipher algorithms
such as AES, 3DES..., hashing and RNG
Hi,
this v2 of the series solves several issues pointed out by Arnd Bergmann
and Arnaud Patard.
Moreover, it drops platform support and relies only on device tree (compile
tested only).
[PATCH v2 1/3] i.MX27: Add clock support for SAHARA2.
[PATCH v2 2/3] crypto: sahara: Add driver for SAHARA2
Signed-off-by: Javier Martin javier.mar...@vista-silicon.com
---
arch/arm/mach-imx/clk-imx27.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 4c1d1e4..0b9664a 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm
SAHARA2 HW module is included in the i.MX27 SoC from
Freescale. It is capable of performing cipher algorithms
such as AES, 3DES..., hashing and RNG too.
This driver provides support for AES-CBC and AES-ECB
by now.
Signed-off-by: Javier Martin javier.mar...@vista-silicon.com
---
drivers/crypto
Hi Arnaud,
thank you for your feedback. Sorry, I always forget to test my drivers
as modules.
I'll address the issues you pointed out, as well as the improvements
suggested by Arnd, for v2.
Regards.
On 23 February 2013 21:16, Arnaud Patard arnaud.pat...@rtp-net.org wrote:
Javier Martin
This series of patches provide AES-ECB and AES-CBC support
for the SAHARA2 cryptographic accelerator which is inside the i.MX27 SoC.
It is expected that more algorithms will be supported in the future.
For testing, a Visstrim M10 board has been used and the code related
to this platform has been
SAHARA2 HW module is included in the i.MX27 SoC from
Freescale. It is capable of performing cipher algorithms
such as AES, 3DES..., hashing and RNG too.
This driver provides support for AES-CBC and AES-ECB
by now.
Signed-off-by: Javier Martin javier.mar...@vista-silicon.com
---
drivers/crypto
Signed-off-by: Javier Martin javier.mar...@vista-silicon.com
---
arch/arm/mach-imx/Kconfig |1 +
arch/arm/mach-imx/mach-imx27_visstrim_m10.c |1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 1ad0d76..d232a56
Hi Arnd,
On 21 February 2013 13:59, Arnd Bergmann a...@arndb.de wrote:
On Thursday 21 February 2013, Javier Martin wrote:
This series of patches provide AES-ECB and AES-CBC support
for the SAHARA2 cryptographic accelerator which is inside the i.MX27 SoC.
It is expected that more algorithms
Hi Arnd,
thanks for your review.
On 21 February 2013 14:13, Arnd Bergmann a...@arndb.de wrote:
On Thursday 21 February 2013, Javier Martin wrote:
+
+struct sahara_dev {
+ struct device *device;
+ void __iomem*regs_base;
+ struct clk *clk_ipg
15 matches
Mail list logo
