sg_sw_sec4.h header is not used by caam/qi, thus remove its inclusion.
Signed-off-by: Horia Geantă <horia.gea...@nxp.com>
---
drivers/crypto/caam/caamalg_qi.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/crypto/caam/caamalg_qi.c b/drivers/crypto/caam/caamalg_qi.c
index 82e9f9
sg_sw_sec4.h header is not used by caam/qi, thus remove its inclusion.
Signed-off-by: Horia Geantă <horia.gea...@nxp.com>
---
drivers/crypto/caam/caamalg_qi.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/crypto/caam/caamalg_qi.c b/drivers/crypto/caam/caamalg_qi.c
index e84c19
sec4_sg_entry structure is used only by helper functions in sg_sw_sec4.h.
Since SEC HW S/G entries are to be manipulated only indirectly, via these
functions, move sec4_sg_entry to the corresponding header.
Signed-off-by: Horia Geantă <horia.gea...@nxp.com>
---
drivers/crypto/caam/
From: Rameshwar Prasad Sahu <rs...@apm.com>
This patch implements support for APM X-Gene SoC CRC32C h/w accelerator.
DMA engine in APM X-Gene SoC is capable of doing CRC32C computations.
Signed-off-by: Rameshwar Prasad Sahu <rs...@apm.com>
---
drivers/crypto/Kconfig|8
This patch implements support for APM X-Gene SoC CRC32C h/w accelerator.
DMA engine in APM X-Gene SoC is capable of doing CRC32C computations.
Signed-off-by: Rameshwar Prasad Sahu <rs...@apm.com>
---
drivers/crypto/Kconfig|8 ++
drivers/crypto/Makefile |1 +
drivers/
On Thu, Aug 20, 2015 at 12:31:44PM +0530, Rameshwar Sahu wrote:
Hi Vinod,
On Thu, Aug 20, 2015 at 11:18 AM, Vinod Koul vinod.k...@intel.com wrote:
On Thu, Jul 30, 2015 at 05:41:07PM +0530, Rameshwar Prasad Sahu wrote:
+ nents = sg_nents(req-src);
+ sg_count = dma_map_sg(dev,
Hi Vinod,
On Thu, Aug 20, 2015 at 11:18 AM, Vinod Koul vinod.k...@intel.com wrote:
On Thu, Jul 30, 2015 at 05:41:07PM +0530, Rameshwar Prasad Sahu wrote:
+ nents = sg_nents(req-src);
+ sg_count = dma_map_sg(dev, req-src, nents, DMA_TO_DEVICE);
+ if (!sg_count) {
+
On Thu, Jul 30, 2015 at 05:41:07PM +0530, Rameshwar Prasad Sahu wrote:
+ nents = sg_nents(req-src);
+ sg_count = dma_map_sg(dev, req-src, nents, DMA_TO_DEVICE);
+ if (!sg_count) {
+ dev_err(dev, Failed to map src sg);
+ return -ENOMEM;
mapping error
On Thu, Jul 30, 2015 at 05:41:07PM +0530, Rameshwar Prasad Sahu wrote:
+ .cra_name = xgene(crc32c),
+ .cra_driver_name= crc32c-xgene,
This looks wrong. If you're implementing crc32c then cra_name
should be just crc32c, i.e., the name of the
On Fri, Jul 31, 2015 at 12:43 PM, Herbert Xu
herb...@gondor.apana.org.au wrote:
On Thu, Jul 30, 2015 at 05:41:07PM +0530, Rameshwar Prasad Sahu wrote:
+ .cra_name = xgene(crc32c),
+ .cra_driver_name= crc32c-xgene,
This looks wrong. If you're
This patch implements support for APM X-Gene SoC CRC32C h/w accelerator.
DMA engine in APM X-Gene SoC is capable of doing CRC32C calculations.
Signed-off-by: Rameshwar Prasad Sahu rs...@apm.com
---
drivers/crypto/Kconfig| 8 ++
drivers/crypto/Makefile | 1 +
drivers/crypto
On Fri, Jun 12, 2015 at 10:58:45AM -0400, Dan Streetman wrote:
Now that the crypto/842.c driver does only software 842 comp/decomp,
and the hardware crypto compressor for 842-nx is located in
drivers/crypto/nx with the NX 842 hw driver, there's no reason for
the nx842.h header to be located
Move the contents of the include/linux/nx842.h header file into the
drivers/crypto/nx/nx-842.h header file. Remove the nx842.h header
file and its entry in the MAINTAINERS file.
The include/linux/nx842.h header originally was there because the
crypto/842.c driver needed it to communicate
Now that the crypto/842.c driver does only software 842 comp/decomp,
and the hardware crypto compressor for 842-nx is located in
drivers/crypto/nx with the NX 842 hw driver, there's no reason for
the nx842.h header to be located in include/linux/ anymore; nobody
should use the NX 842 hw driver
Move interrupt related macros in talitos2.h as they are specific to SEC2
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 58 -
drivers/crypto/talitos2.h | 60 +++
2
Move hash chain handling into talitos2.h as only SEC2 has sg chaining
capatibility
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 34 --
drivers/crypto/talitos2.h | 34 ++
2 files changed
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 4 +---
drivers/crypto/talitos2.h | 2 ++
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 8b627d0..0262e75 100644
--- a/drivers/crypto
Move reset/init helpers init talitos2.h as they are specific to SEC2
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 19 ---
drivers/crypto/talitos2.h | 20
2 files changed, 20 insertions(+), 19 deletions(-)
diff
Move reset/init helpers init talitos2.h as they are specific to SEC2
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 19 ---
drivers/crypto/talitos2.h | 20
2 files changed, 20 insertions(+), 19 deletions(-)
diff
Move interrupt related macros in talitos2.h as they are specific to SEC2
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 58 -
drivers/crypto/talitos2.h | 60 +++
2
Move hash chain handling into talitos2.h as only SEC2 has sg chaining
capatibility
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 34 --
drivers/crypto/talitos2.h | 34 ++
2 files changed
Signed-off-by: Christophe Leroy christophe.le...@c-s.fr
---
drivers/crypto/talitos.c | 4 +---
drivers/crypto/talitos2.h | 2 ++
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index 6c1f6f1..9f75ec9 100644
--- a/drivers/crypto
Please Revert back, your assistance is needed.
---
The Exhibitor at innoTrans, Berlin 2014
Hall : 15.1 / Stand no : 109
http://www.virtualmarket.innotrans.de/?Action=showCompanyid=346242
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sec4_sg_entry structure is used only by helper functions in sg_sw_sec4.h.
Since SEC HW S/G entries are to be manipulated only indirectly, via these
functions, move sec4_sg_entry to the corresponding header.
Signed-off-by: Horia Geanta horia.gea...@freescale.com
---
drivers/crypto/caam/desc.h
-
-#if defined(__cplusplus)
-extern C {
-#endif
-
-#ifndef BRG_UI8
-# define BRG_UI8
- typedef unsigned char uint_8t;
-#endif
-
-#ifndef BRG_UI16
-# define BRG_UI16
- typedef unsigned short uint_16t;
-#endif
-
-#ifndef BRG_UI32
-# define BRG_UI32
-#define li_32(h) 0x##h##u
- typedef unsigned
-
-#if defined(__cplusplus)
-extern C {
-#endif
-
-#ifndef BRG_UI8
-# define BRG_UI8
- typedef unsigned char uint_8t;
-#endif
-
-#ifndef BRG_UI16
-# define BRG_UI16
- typedef unsigned short uint_16t;
-#endif
-
-#ifndef BRG_UI32
-# define BRG_UI32
-#define li_32(h) 0x##h##u
- typedef unsigned
Currently, all workqueue workers which have negative nice value has
'H' postfixed to their names. This is necessary for per-cpu workers
as they use the CPU number instead of pool-id to identify the pool
and the 'H' postfix is the only thing distinguishing normal and
highpri workers.
As workers
Currently, all workqueue workers which have negative nice value has
'H' postfixed to their names. This is necessary for per-cpu workers
as they use the CPU number instead of pool-id to identify the pool
and the 'H' postfix is the only thing distinguishing normal and
highpri workers.
As workers
Code was needlessly checking the s/w job ring when there
would be nothing to process if the h/w's output completion
ring were empty anyway.
Signed-off-by: Kim Phillips kim.phill...@freescale.com
---
drivers/crypto/caam/jr.c | 17 +
1 file changed, 5 insertions(+), 12 deletions
++
arch/x86/include/asm/crypto/serpent-sse2.h | 63
arch/x86/include/asm/serpent-avx.h | 32 --
arch/x86/include/asm/serpent-sse2.h| 63
6 files changed, 97 insertions(+), 97 deletions(-)
create mode 100644 arch
On Mon, Dec 12, 2011 at 02:59:09PM -0600, Kim Phillips wrote:
The first patch in the series fixes a boottime oops on SEC h/w v.2.0.
The rest are minor cleanups.
The fourth - crypto: caam - desc.h - convert spaces to tabs -
is the result of running unexpand -a on desc.h, and may exceed list
crypto_async_request *areq received is
corrupted. Since this API is not involved when I use s/w crypto I do
not have any working example to follow. Just wondering if anyone come
across any such problem or issue while developing H/W crypto driver.
I am using Linux 2.6.37 for my development
Hi All
I am trying to work Openswan IPsec(2.6.33) (NETKEY) with NSS H/W
cryptodrivers for ARM cortex based SoC running linux 2.6.37. I am
facing this weird problem where when I ping I see (wireshark) ESP
packets going both side but I am not receiving anything on either
side. See the log below.I
and PCLMULQDQ
accelerated GHASH implementation.
v3:
- Renamed to irq_fpu_usable to reflect the purpose of the function.
v2:
- Renamed to irq_is_fpu_using to reflect the real situation.
Signed-off-by: Huang Ying ying.hu...@intel.com
CC: H. Peter Anvin h...@zytor.com
---
arch/x86/crypto/aesni-intel_glue.c
On Wed, Aug 05, 2009 at 11:27:02PM -0700, H. Peter Anvin wrote:
Herbert Xu wrote:
Peter, do you want to apply this patch in your tree or would
you prefer for it to go through my tree along with the rest of
the series?
I'll take it tomorrow... want to double-check that we don't have any
* Huang Ying ying.hu...@intel.com wrote:
This is used by AES-NI accelerated AES implementation and PCLMULQDQ
accelerated GHASH implementation.
Signed-off-by: Huang Ying ying.hu...@intel.com
---
arch/x86/crypto/aesni-intel_glue.c |7 ---
arch/x86/include/asm/i387.h
spurious #TS faults
due to broken design of the Padlock instructions. The AES and PCLMUL
instructions actually use SSE registers and so will require different
structure.
-hpa
--
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel. I don't speak on their behalf
On Wed, Jun 17, 2009 at 10:06:44AM -0700, H. Peter Anvin wrote:
Ingo Molnar wrote:
+static inline int kernel_fpu_using(void)
+{
+ if (in_interrupt() !(read_cr0() X86_CR0_TS))
+ return 1;
+ return 0;
+}
+
Looks sane to me. Herbert, do you ack it?
Ack. Please
Herbert Xu wrote:
On Wed, Jun 17, 2009 at 10:06:44AM -0700, H. Peter Anvin wrote:
Huang: if I recall correctly, these functions were originally designed
to deal with the fact that VIA processors generate spurious #TS faults
due to broken design of the Padlock instructions. The AES
() fpu_using();
}
Yes, looks good. I'll pull in the patch as soon as I get it.
-hpa
--
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel. I don't speak on their behalf.
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the body
This is used by AES-NI accelerated AES implementation and PCLMULQDQ
accelerated GHASH implementation.
Signed-off-by: Huang Ying ying.hu...@intel.com
---
arch/x86/crypto/aesni-intel_glue.c |7 ---
arch/x86/include/asm/i387.h|7 +++
2 files changed, 7 insertions(+), 7
From: Kim Phillips [EMAIL PROTECTED]
SEC version 2.1 and above adds the capability to do the IPSec ICV
memcmp in h/w. Results of the cmp are written back in the descriptor
header, along with the done status. A new callback is added that
checks these ICCR bits instead of performing the memcmp
Signed-off-by: Kim Phillips [EMAIL PROTECTED]
---
drivers/crypto/talitos.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/crypto/talitos.c b/drivers/crypto/talitos.c
index f301e95..ce4787e 100644
--- a/drivers/crypto/talitos.c
+++ b/drivers/crypto/talitos.c
@@
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