Re: [PATCH 3/3] drivers: crypto: Enable CPT options crypto for build

[kbuild test robot]

Hi George,

[auto build test ERROR on cryptodev/master]
[also build test ERROR on v4.9-rc5 next-20161117]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/gcherianv-gmail-com/Add-Support-for-Cavium-Cryptographic-Accelerarion-Unit/20161119-005337
base:   
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git master
config: arm64-allmodconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget 
https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
 -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64 

All error/warnings (new ones prefixed by >>):

warning: (CRYPTO_DEV_CPT) selects HW_RANDOM_OCTEON which has unmet direct 
dependencies (HW_RANDOM && CAVIUM_OCTEON_SOC)
   In file included from drivers/crypto/cavium/cpt/cpt_common.h:27:0,
from drivers/crypto/cavium/cpt/cpt.h:12,
from drivers/crypto/cavium/cpt/cpt_main.c:19:
>> drivers/crypto/cavium/cpt/cpt_hw_types.h:439:2: warning: no semicolon at end 
>> of struct or union
 } s;
 ^
>> drivers/crypto/cavium/cpt/cpt_hw_types.h:608:3: error: expected ',', ';' or 
>> '}' before 'uint64_t'
  uint64_t reserved_0_5:6;
  ^~~~
   drivers/crypto/cavium/cpt/cpt_main.c:236:13: warning: 
'cpt_enable_all_interrupts' defined but not used [-Wunused-function]
static void cpt_enable_all_interrupts(struct cpt_device *cpt)
^
--
   In file included from drivers/crypto/cavium/cpt/cpt_common.h:27:0,
from drivers/crypto/cavium/cpt/cpt.h:12,
from drivers/crypto/cavium/cpt/cpt_pf_mbox.c:11:
>> drivers/crypto/cavium/cpt/cpt_hw_types.h:439:2: warning: no semicolon at end 
>> of struct or union
 } s;
 ^
>> drivers/crypto/cavium/cpt/cpt_hw_types.h:608:3: error: expected ',', ';' or 
>> '}' before 'uint64_t'
  uint64_t reserved_0_5:6;
  ^~~~
--
>> drivers/char/hw_random/octeon-rng.c:19:31: fatal error: asm/octeon/octeon.h: 
>> No such file or directory
#include 
  ^
   compilation terminated.

vim +608 drivers/crypto/cavium/cpt/cpt_hw_types.h

fcb2dbd1 George Cherian 2016-11-18  433 uint64_t 
reserved_48_63:16;
fcb2dbd1 George Cherian 2016-11-18  434 uint64_t bstatus:48
fcb2dbd1 George Cherian 2016-11-18  435  #else /* Word 0 - Little Endian */
fcb2dbd1 George Cherian 2016-11-18  436 uint64_t bstatus:48;
fcb2dbd1 George Cherian 2016-11-18  437 uint64_t 
reserved_48_63:16;
fcb2dbd1 George Cherian 2016-11-18  438  #endif /* Word 0 - End */
fcb2dbd1 George Cherian 2016-11-18 @439 } s;
fcb2dbd1 George Cherian 2016-11-18  440 struct 
cptx_pf_exe_bist_status_cn81xx {
fcb2dbd1 George Cherian 2016-11-18  441  #if defined(__BIG_ENDIAN_BITFIELD) /* 
Word 0 - Big Endian */
fcb2dbd1 George Cherian 2016-11-18  442 uint64_t 
reserved_16_63:48;
fcb2dbd1 George Cherian 2016-11-18  443 uint64_t bstatus:16;
fcb2dbd1 George Cherian 2016-11-18  444  #else /* Word 0 - Little Endian */
fcb2dbd1 George Cherian 2016-11-18  445 uint64_t bstatus:16;
fcb2dbd1 George Cherian 2016-11-18  446 uint64_t 
reserved_16_63:48;
fcb2dbd1 George Cherian 2016-11-18  447  #endif /* Word 0 - End */
fcb2dbd1 George Cherian 2016-11-18  448 } cn81xx;
fcb2dbd1 George Cherian 2016-11-18  449  };
fcb2dbd1 George Cherian 2016-11-18  450  
fcb2dbd1 George Cherian 2016-11-18  451  /**
fcb2dbd1 George Cherian 2016-11-18  452   * Register (NCB) cpt#_pf_exe_ctl
fcb2dbd1 George Cherian 2016-11-18  453   *
fcb2dbd1 George Cherian 2016-11-18  454   * CPT PF Engine Control Register
fcb2dbd1 George Cherian 2016-11-18  455   * This register enables the engines.
fcb2dbd1 George Cherian 2016-11-18  456   * cptx_pf_exe_ctl_s
fcb2dbd1 George Cherian 2016-11-18  457   * Word0
fcb2dbd1 George Cherian 2016-11-18  458   *  enable:64 [63:0](R/W) Individual 
enables for each of the engines.
fcb2dbd1 George Cherian 2016-11-18  459   */
fcb2dbd1 George Cherian 2016-11-18  460  union cptx_pf_exe_ctl {
fcb2dbd1 George Cherian 2016-11-18  461 uint64_t u;
fcb2dbd1 George Cherian 2016-11-18  462 struct cptx_pf_exe_ctl_s {
fcb2dbd1 George Cherian 2016-11-18  463  #if defined(__BIG_ENDIAN_BITFIELD) /* 
Word 0 - Big Endian */
fcb2dbd1 George Cherian 2016-11-18  464 uint64_t enable:64;
fcb2dbd1 George Cherian 2016-11-18  465  #else /* Word 0 - Little Endian */
fcb2dbd1 George Cherian 2016-11-18  466 uint64_t enable:64;
fcb2dbd1 George Cherian 2016-11-18  467  #endif /* Word 0 - End */
fcb2dbd1 George Cherian 2016-11-18  468 } s;
fcb2dbd1 George Cherian 2016-11-18  469  };

Re: [PATCH 1/3] drivers: crypto: Add Support for Octeon-tx CPT Engine

[George Cherian]

Hi David,

Thanks for the review.
On Saturday 19 November 2016 12:25 AM, David Daney wrote:

On 11/18/2016 07:00 AM, gcheri...@gmail.com wrote:

From: George Cherian 

Enable the Physical Function diver for the Cavium Crypto Engine (CPT)
found in Octeon-tx series of SoC's. CPT is the Cryptographic 
Acceleration

Unit. CPT includes microcoded GigaCypher symmetric engines (SEs) and
asymmetric engines (AEs).

Signed-off-by: George Cherian 



How was this tested?

Using ecryptfs and dm-crypt.




---
  drivers/crypto/cavium/cpt/Kconfig|  22 +
  drivers/crypto/cavium/cpt/Makefile   |   2 +
  drivers/crypto/cavium/cpt/cpt.h  |  90 +++
  drivers/crypto/cavium/cpt/cpt_common.h   | 377 +
  drivers/crypto/cavium/cpt/cpt_hw_types.h | 940 
+++
  drivers/crypto/cavium/cpt/cpt_main.c | 891 
+

  drivers/crypto/cavium/cpt/cpt_pf_mbox.c  | 174 ++
  7 files changed, 2496 insertions(+)
  create mode 100644 drivers/crypto/cavium/cpt/Kconfig
  create mode 100644 drivers/crypto/cavium/cpt/Makefile
  create mode 100644 drivers/crypto/cavium/cpt/cpt.h
  create mode 100644 drivers/crypto/cavium/cpt/cpt_common.h
  create mode 100644 drivers/crypto/cavium/cpt/cpt_hw_types.h
  create mode 100644 drivers/crypto/cavium/cpt/cpt_main.c
  create mode 100644 drivers/crypto/cavium/cpt/cpt_pf_mbox.c

diff --git a/drivers/crypto/cavium/cpt/Kconfig 
b/drivers/crypto/cavium/cpt/Kconfig

new file mode 100644
index 000..8fe3f44
--- /dev/null
+++ b/drivers/crypto/cavium/cpt/Kconfig
@@ -0,0 +1,22 @@
+#
+# Cavium crypto device configuration
+#
+
+config CRYPTO_DEV_CPT
+tristate
+select HW_RANDOM_OCTEON


This makes no sense.  HW_RANDOM_OCTEON is for a mips64 based SOC and 
isn't present on devices that have this crypto block.  Why select this?


Yeah true... I actually wanted to this one instead 
|CONFIG_HW_RANDOM_CAVIUM|



+select CRYPTO_AES
+select CRYPTO_DES
+select CRYPTO_BLKCIPHER
+select FW_LOADER
+
+config OCTEONTX_CPT_PF
+tristate "Octeon-tx CPT Physical function driver"
+depends on ARCH_THUNDER
+select CRYPTO_DEV_CPT
+help
+  Support for Cavium CPT block found in octeon-tx series of
+  processors.
+
+  To compile this as a module, choose M here: the module will be
+  called cptpf.
diff --git a/drivers/crypto/cavium/cpt/Makefile 
b/drivers/crypto/cavium/cpt/Makefile

new file mode 100644
index 000..bf758e2
--- /dev/null
+++ b/drivers/crypto/cavium/cpt/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_OCTEONTX_CPT_PF) += cptpf.o
+cptpf-objs := cpt_main.o cpt_pf_mbox.o
diff --git a/drivers/crypto/cavium/cpt/cpt.h 
b/drivers/crypto/cavium/cpt/cpt.h

new file mode 100644
index 000..63d12da
--- /dev/null
+++ b/drivers/crypto/cavium/cpt/cpt.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2016 Cavium, Inc.
+ *
+ * This program is free software; you can redistribute it and/or 
modify it

+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ */
+
+#ifndef __CPT_H
+#define __CPT_H
+
+#include "cpt_common.h"
+
+#define BASE_PROC_DIR"cavium"
+
+#define PF  0
+#define VF  1
+
+struct cpt_device;
+
+struct microcode {
+uint8_t  is_mc_valid;


s/uint8_t/u8/  ??

That could be done everywhere.

will do


[...]
diff --git a/drivers/crypto/cavium/cpt/cpt_common.h 
b/drivers/crypto/cavium/cpt/cpt_common.h

new file mode 100644
index 000..351ed4a
--- /dev/null
+++ b/drivers/crypto/cavium/cpt/cpt_common.h
@@ -0,0 +1,377 @@
+/*
+ * Copyright (C) 2016 Cavium, Inc.
+ *
+ * This program is free software; you can redistribute it and/or 
modify it

+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ */
+
+#ifndef __CPT_COMMON_H
+#define __CPT_COMMON_H
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "cpt_hw_types.h"
+
+/* configuration space offsets */
+#ifndef PCI_VENDOR_ID
+#define PCI_VENDOR_ID 0x00 /* 16 bits */
+#endif
+#ifndef PCI_DEVICE_ID
+#define PCI_DEVICE_ID 0x02 /* 16 bits */
+#endif
+#ifndef PCI_REVISION_ID
+#define PCI_REVISION_ID 0x08 /* Revision ID */
+#endif
+#ifndef PCI_CAPABILITY_LIST
+#define PCI_CAPABILITY_LIST 0x34 /* first capability list entry */
+#endif
+


Standard PCI core functions give you access to all that information, 
use pdev->device, pdev->revision, etc. instead of reinventing the 
wheel here with all these #defines.




+/* Device ID */
+#define PCI_VENDOR_ID_CAVIUM 0x177d


This is defined in pci_ids.h, use value from there instead of placing 
a duplicate definition here.



okay will remove them

+#define CPT_81XX_PCI_PF_DEVICE_ID 0xa040
+#define CPT_81XX_PCI_VF_DEVICE_ID 0xa041
+
+#define PASS_1_0 0x0
+
+/* CPT Models ((Device ID<<16)|Revision ID) */
+/* CPT models */

Re: [PATCH 1/3] drivers: crypto: Add Support for Octeon-tx CPT Engine

[David Daney]

On 11/18/2016 07:00 AM, gcheri...@gmail.com wrote:

From: George Cherian 

Enable the Physical Function diver for the Cavium Crypto Engine (CPT)
found in Octeon-tx series of SoC's. CPT is the Cryptographic Acceleration
Unit. CPT includes microcoded GigaCypher symmetric engines (SEs) and
asymmetric engines (AEs).

Signed-off-by: George Cherian 



How was this tested?


---
  drivers/crypto/cavium/cpt/Kconfig|  22 +
  drivers/crypto/cavium/cpt/Makefile   |   2 +
  drivers/crypto/cavium/cpt/cpt.h  |  90 +++
  drivers/crypto/cavium/cpt/cpt_common.h   | 377 +
  drivers/crypto/cavium/cpt/cpt_hw_types.h | 940 +++
  drivers/crypto/cavium/cpt/cpt_main.c | 891 +
  drivers/crypto/cavium/cpt/cpt_pf_mbox.c  | 174 ++
  7 files changed, 2496 insertions(+)
  create mode 100644 drivers/crypto/cavium/cpt/Kconfig
  create mode 100644 drivers/crypto/cavium/cpt/Makefile
  create mode 100644 drivers/crypto/cavium/cpt/cpt.h
  create mode 100644 drivers/crypto/cavium/cpt/cpt_common.h
  create mode 100644 drivers/crypto/cavium/cpt/cpt_hw_types.h
  create mode 100644 drivers/crypto/cavium/cpt/cpt_main.c
  create mode 100644 drivers/crypto/cavium/cpt/cpt_pf_mbox.c

diff --git a/drivers/crypto/cavium/cpt/Kconfig 
b/drivers/crypto/cavium/cpt/Kconfig
new file mode 100644
index 000..8fe3f44
--- /dev/null
+++ b/drivers/crypto/cavium/cpt/Kconfig
@@ -0,0 +1,22 @@
+#
+# Cavium crypto device configuration
+#
+
+config CRYPTO_DEV_CPT
+   tristate
+   select HW_RANDOM_OCTEON


This makes no sense.  HW_RANDOM_OCTEON is for a mips64 based SOC and 
isn't present on devices that have this crypto block.  Why select this?




+   select CRYPTO_AES
+   select CRYPTO_DES
+   select CRYPTO_BLKCIPHER
+   select FW_LOADER
+
+config OCTEONTX_CPT_PF
+   tristate "Octeon-tx CPT Physical function driver"
+   depends on ARCH_THUNDER
+   select CRYPTO_DEV_CPT
+   help
+ Support for Cavium CPT block found in octeon-tx series of
+ processors.
+
+ To compile this as a module, choose M here: the module will be
+ called cptpf.
diff --git a/drivers/crypto/cavium/cpt/Makefile 
b/drivers/crypto/cavium/cpt/Makefile
new file mode 100644
index 000..bf758e2
--- /dev/null
+++ b/drivers/crypto/cavium/cpt/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_OCTEONTX_CPT_PF) += cptpf.o
+cptpf-objs := cpt_main.o cpt_pf_mbox.o
diff --git a/drivers/crypto/cavium/cpt/cpt.h b/drivers/crypto/cavium/cpt/cpt.h
new file mode 100644
index 000..63d12da
--- /dev/null
+++ b/drivers/crypto/cavium/cpt/cpt.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2016 Cavium, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ */
+
+#ifndef __CPT_H
+#define __CPT_H
+
+#include "cpt_common.h"
+
+#define BASE_PROC_DIR  "cavium"
+
+#define PF  0
+#define VF  1
+
+struct cpt_device;
+
+struct microcode {
+   uint8_t  is_mc_valid;


s/uint8_t/u8/  ??

That could be done everywhere.

[...]

diff --git a/drivers/crypto/cavium/cpt/cpt_common.h 
b/drivers/crypto/cavium/cpt/cpt_common.h
new file mode 100644
index 000..351ed4a
--- /dev/null
+++ b/drivers/crypto/cavium/cpt/cpt_common.h
@@ -0,0 +1,377 @@
+/*
+ * Copyright (C) 2016 Cavium, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ */
+
+#ifndef __CPT_COMMON_H
+#define __CPT_COMMON_H
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "cpt_hw_types.h"
+
+/* configuration space offsets */
+#ifndef PCI_VENDOR_ID
+#define PCI_VENDOR_ID 0x00 /* 16 bits */
+#endif
+#ifndef PCI_DEVICE_ID
+#define PCI_DEVICE_ID 0x02 /* 16 bits */
+#endif
+#ifndef PCI_REVISION_ID
+#define PCI_REVISION_ID 0x08 /* Revision ID */
+#endif
+#ifndef PCI_CAPABILITY_LIST
+#define PCI_CAPABILITY_LIST 0x34 /* first capability list entry */
+#endif
+


Standard PCI core functions give you access to all that information, use 
pdev->device, pdev->revision, etc. instead of reinventing the wheel here 
with all these #defines.




+/* Device ID */
+#define PCI_VENDOR_ID_CAVIUM 0x177d


This is defined in pci_ids.h, use value from there instead of placing a 
duplicate definition here.



+#define CPT_81XX_PCI_PF_DEVICE_ID 0xa040
+#define CPT_81XX_PCI_VF_DEVICE_ID 0xa041
+
+#define PASS_1_0 0x0
+
+/* CPT Models ((Device ID<<16)|Revision ID) */
+/* CPT models */
+#define CPT_81XX_PASS1_0 ((CPT_81XX_PCI_PF_DEVICE_ID << 8) | PASS_1_0)
+#define CPTVF_81XX_PASS1_0 ((CPT_81XX_PCI_VF_DEVICE_ID << 8) | PASS_1_0)
+
+#define PF 0
+#define VF 1
+
+#define DEFAULT_DEVICE_QUEUES 

Re: [PATCH net-next] cxgb4: Allocate Tx queues dynamically

[David Miller]

From: Atul Gupta 
Date: Fri, 18 Nov 2016 16:37:40 +0530

> From: Hariprasad Shenai 
> 
> Allocate resources dynamically for Upper layer driver's (ULD) like
> cxgbit, iw_cxgb4, cxgb4i and chcr. The resources allocated include Tx
> queues which are allocated when ULD register with cxgb4 driver and freed
> while un-registering. The Tx queues which are shared by ULD shall be
> allocated by first registering driver and un-allocated by last
> unregistering driver.
> 
> Signed-off-by: Atul Gupta 

Applied.
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[PATCH] hw_random: Make explicit that max >= 32 always

[PrasannaKumar Muralidharan]

As hw_random core calls ->read with max > 32 or more, make it explicit.
Also remove checks involving 'max' being less than 8.

Signed-off-by: PrasannaKumar Muralidharan 
---
 drivers/char/hw_random/msm-rng.c | 4 
 drivers/char/hw_random/pic32-rng.c   | 3 ---
 drivers/char/hw_random/pseries-rng.c | 5 ++---
 include/linux/hw_random.h| 3 +--
 4 files changed, 3 insertions(+), 12 deletions(-)

diff --git a/drivers/char/hw_random/msm-rng.c b/drivers/char/hw_random/msm-rng.c
index 96fb986..841fee8 100644
--- a/drivers/char/hw_random/msm-rng.c
+++ b/drivers/char/hw_random/msm-rng.c
@@ -90,10 +90,6 @@ static int msm_rng_read(struct hwrng *hwrng, void *data, 
size_t max, bool wait)
/* calculate max size bytes to transfer back to caller */
maxsize = min_t(size_t, MAX_HW_FIFO_SIZE, max);
 
-   /* no room for word data */
-   if (maxsize < WORD_SZ)
-   return 0;
-
ret = clk_prepare_enable(rng->clk);
if (ret)
return ret;
diff --git a/drivers/char/hw_random/pic32-rng.c 
b/drivers/char/hw_random/pic32-rng.c
index 11dc9b7..9b5e68a 100644
--- a/drivers/char/hw_random/pic32-rng.c
+++ b/drivers/char/hw_random/pic32-rng.c
@@ -62,9 +62,6 @@ static int pic32_rng_read(struct hwrng *rng, void *buf, 
size_t max,
u32 t;
unsigned int timeout = RNG_TIMEOUT;
 
-   if (max < 8)
-   return 0;
-
do {
t = readl(priv->base + RNGRCNT) & RCNT_MASK;
if (t == 64) {
diff --git a/drivers/char/hw_random/pseries-rng.c 
b/drivers/char/hw_random/pseries-rng.c
index 63ce51d..d9f46b4 100644
--- a/drivers/char/hw_random/pseries-rng.c
+++ b/drivers/char/hw_random/pseries-rng.c
@@ -28,7 +28,6 @@
 static int pseries_rng_read(struct hwrng *rng, void *data, size_t max, bool 
wait)
 {
u64 buffer[PLPAR_HCALL_BUFSIZE];
-   size_t size = max < 8 ? max : 8;
int rc;
 
rc = plpar_hcall(H_RANDOM, (unsigned long *)buffer);
@@ -36,10 +35,10 @@ static int pseries_rng_read(struct hwrng *rng, void *data, 
size_t max, bool wait
pr_err_ratelimited("H_RANDOM call failed %d\n", rc);
return -EIO;
}
-   memcpy(data, buffer, size);
+   memcpy(data, buffer, 8);
 
/* The hypervisor interface returns 64 bits */
-   return size;
+   return 8;
 }
 
 /**
diff --git a/include/linux/hw_random.h b/include/linux/hw_random.h
index 34a0dc1..bee0827 100644
--- a/include/linux/hw_random.h
+++ b/include/linux/hw_random.h
@@ -30,8 +30,7 @@
  * Must not be NULL.*OBSOLETE*
  * @read:  New API. drivers can fill up to max bytes of data
  * into the buffer. The buffer is aligned for any type
- * and max is guaranteed to be >= to that alignment
- * (either 4 or 8 depending on architecture).
+ * and max is a multiple of 4 and >= 32 bytes.
  * @priv:  Private data, for use by the RNG driver.
  * @quality:   Estimation of true entropy in RNG's bitstream
  * (per mill).
-- 
2.9.3

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[PATCH 1/3] drivers: crypto: Add Support for Octeon-tx CPT Engine

[gcherianv]

From: George Cherian 

Enable the Physical Function diver for the Cavium Crypto Engine (CPT)
found in Octeon-tx series of SoC's. CPT is the Cryptographic Acceleration
Unit. CPT includes microcoded GigaCypher symmetric engines (SEs) and
asymmetric engines (AEs).

Signed-off-by: George Cherian 
---
 drivers/crypto/cavium/cpt/Kconfig|  22 +
 drivers/crypto/cavium/cpt/Makefile   |   2 +
 drivers/crypto/cavium/cpt/cpt.h  |  90 +++
 drivers/crypto/cavium/cpt/cpt_common.h   | 377 +
 drivers/crypto/cavium/cpt/cpt_hw_types.h | 940 +++
 drivers/crypto/cavium/cpt/cpt_main.c | 891 +
 drivers/crypto/cavium/cpt/cpt_pf_mbox.c  | 174 ++
 7 files changed, 2496 insertions(+)
 create mode 100644 drivers/crypto/cavium/cpt/Kconfig
 create mode 100644 drivers/crypto/cavium/cpt/Makefile
 create mode 100644 drivers/crypto/cavium/cpt/cpt.h
 create mode 100644 drivers/crypto/cavium/cpt/cpt_common.h
 create mode 100644 drivers/crypto/cavium/cpt/cpt_hw_types.h
 create mode 100644 drivers/crypto/cavium/cpt/cpt_main.c
 create mode 100644 drivers/crypto/cavium/cpt/cpt_pf_mbox.c

diff --git a/drivers/crypto/cavium/cpt/Kconfig 
b/drivers/crypto/cavium/cpt/Kconfig
new file mode 100644
index 000..8fe3f44
--- /dev/null
+++ b/drivers/crypto/cavium/cpt/Kconfig
@@ -0,0 +1,22 @@
+#
+# Cavium crypto device configuration
+#
+
+config CRYPTO_DEV_CPT
+   tristate
+   select HW_RANDOM_OCTEON
+   select CRYPTO_AES
+   select CRYPTO_DES
+   select CRYPTO_BLKCIPHER
+   select FW_LOADER
+
+config OCTEONTX_CPT_PF
+   tristate "Octeon-tx CPT Physical function driver"
+   depends on ARCH_THUNDER
+   select CRYPTO_DEV_CPT
+   help
+ Support for Cavium CPT block found in octeon-tx series of
+ processors.
+
+ To compile this as a module, choose M here: the module will be
+ called cptpf.
diff --git a/drivers/crypto/cavium/cpt/Makefile 
b/drivers/crypto/cavium/cpt/Makefile
new file mode 100644
index 000..bf758e2
--- /dev/null
+++ b/drivers/crypto/cavium/cpt/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_OCTEONTX_CPT_PF) += cptpf.o
+cptpf-objs := cpt_main.o cpt_pf_mbox.o
diff --git a/drivers/crypto/cavium/cpt/cpt.h b/drivers/crypto/cavium/cpt/cpt.h
new file mode 100644
index 000..63d12da
--- /dev/null
+++ b/drivers/crypto/cavium/cpt/cpt.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2016 Cavium, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ */
+
+#ifndef __CPT_H
+#define __CPT_H
+
+#include "cpt_common.h"
+
+#define BASE_PROC_DIR  "cavium"
+
+#define PF  0
+#define VF  1
+
+struct cpt_device;
+
+struct microcode {
+   uint8_t  is_mc_valid;
+   uint8_t  is_ae;
+   uint8_t  group;
+   uint32_t code_size;
+   void*code;
+   uint8_t  num_cores;
+   uint64_t core_mask_low; /* Used as long as num # cores are <= 64 */
+   uint64_t core_mask_hi;  /* Unused for now */
+   uint8_t  version[32];
+
+   /* Base info */
+   dma_addr_t dma;
+   dma_addr_t phys_base;
+   void *base;
+};
+
+#define VF_STATE_DOWN  (0)
+#define VF_STATE_UP(1)
+
+struct cpt_vf_info {
+   uint8_t state;
+   uint8_t priority;
+   uint32_t qlen;
+   union cpt_chipid_vfid id;
+};
+
+/**
+ * cpt device structure
+ */
+struct cpt_device {
+   uint32_t chip_id; /**< CPT Device ID */
+   uint16_t core_freq; /**< CPT Device Frequency */
+   uint16_t flags; /**< Flags to hold device status bits */
+   uint8_t idx; /**< Device Index (0...MAX_CPT_DEVICES) */
+   uint8_t num_vf_en; /**< Number of VFs enabled (0...CPT_MAX_VF_NUM) */
+
+   struct cpt_vf_info vfinfo[CPT_MAX_VF_NUM]; /* Per VF info */
+   uint8_t next_mc_idx; /**< next microcode index */
+   uint8_t next_group;
+
+   uint8_t max_se_cores;
+   uint8_t max_ae_cores;
+   uint8_t avail_se_cores;
+   uint8_t avail_ae_cores;
+
+   void __iomem *reg_base; /* Register start address */
+
+   /* MSI-X */
+   bool msix_enabled;
+   uint8_t num_vec;
+   struct msix_entry msix_entries[CPT_PF_MSIX_VECTORS];
+   bool irq_allocated[CPT_PF_MSIX_VECTORS];
+
+   bool mbx_lock[CPT_MAX_VF_NUM]; /* Mailbox locks per VF */
+
+   struct pci_dev *pdev; /**< pci device handle */
+   void *proc; /**< proc dir */
+   struct microcode mcode[CPT_MAX_CORE_GROUPS];
+};
+
+struct cpt_device_list {
+   /* device list lock */
+   spinlock_t lock;
+   uint32_t nr_device;
+   struct cpt_device *device_ptr[MAX_CPT_DEVICES];
+};
+
+void cpt_mbox_intr_handler(struct cpt_device *cpt, int mbx);
+#endif /* __CPT_H */
diff --git a/drivers/crypto/cavium/cpt/cpt_common.h 
b/drivers/crypto/cavium/cpt/cpt_common.h
new file mode 100644
index 

[PATCH 2/3] drivers: crypto: Add the Virtual Function driver for CPT

[gcherianv]

From: George Cherian 

Enable the CPT VF driver. CPT is the cryptographic Accelaration Unit
in Octeon-tx series of processors.

Signed-off-by: George Cherian 
---
 drivers/crypto/cavium/cpt/Kconfig|   10 +
 drivers/crypto/cavium/cpt/Makefile   |2 +
 drivers/crypto/cavium/cpt/cptvf.h|  255 +++
 drivers/crypto/cavium/cpt/cptvf_algs.c   |  446 +++
 drivers/crypto/cavium/cpt/cptvf_algs.h   |  159 
 drivers/crypto/cavium/cpt/cptvf_main.c   | 1038 ++
 drivers/crypto/cavium/cpt/cptvf_mbox.c   |  208 ++
 drivers/crypto/cavium/cpt/cptvf_reqmanager.c |  655 
 drivers/crypto/cavium/cpt/request_manager.h  |  221 ++
 9 files changed, 2994 insertions(+)
 create mode 100644 drivers/crypto/cavium/cpt/cptvf.h
 create mode 100644 drivers/crypto/cavium/cpt/cptvf_algs.c
 create mode 100644 drivers/crypto/cavium/cpt/cptvf_algs.h
 create mode 100644 drivers/crypto/cavium/cpt/cptvf_main.c
 create mode 100644 drivers/crypto/cavium/cpt/cptvf_mbox.c
 create mode 100644 drivers/crypto/cavium/cpt/cptvf_reqmanager.c
 create mode 100644 drivers/crypto/cavium/cpt/request_manager.h

diff --git a/drivers/crypto/cavium/cpt/Kconfig 
b/drivers/crypto/cavium/cpt/Kconfig
index 8fe3f44..d8c3f48 100644
--- a/drivers/crypto/cavium/cpt/Kconfig
+++ b/drivers/crypto/cavium/cpt/Kconfig
@@ -20,3 +20,13 @@ config OCTEONTX_CPT_PF
 
  To compile this as a module, choose M here: the module will be
  called cptpf.
+config OCTEONTX_CPT_VF
+   tristate "Octeon-tx CPT Virtual function driver"
+   depends on ARCH_THUNDER
+   select CRYPTO_DEV_CPT
+   help
+ Support for Cavium CPT Virtual function found in octeon-tx
+ series of processors.
+
+ To compile this as a module, choose M here: the module will be
+ called cptvf.
diff --git a/drivers/crypto/cavium/cpt/Makefile 
b/drivers/crypto/cavium/cpt/Makefile
index bf758e2..6f70b15 100644
--- a/drivers/crypto/cavium/cpt/Makefile
+++ b/drivers/crypto/cavium/cpt/Makefile
@@ -1,2 +1,4 @@
 obj-$(CONFIG_OCTEONTX_CPT_PF) += cptpf.o
 cptpf-objs := cpt_main.o cpt_pf_mbox.o
+obj-$(CONFIG_OCTEONTX_CPT_VF) += cptvf.o
+cptvf-objs := cptvf_main.o cptvf_reqmanager.o cptvf_mbox.o cptvf_algs.o
diff --git a/drivers/crypto/cavium/cpt/cptvf.h 
b/drivers/crypto/cavium/cpt/cptvf.h
new file mode 100644
index 000..1fafea8
--- /dev/null
+++ b/drivers/crypto/cavium/cpt/cptvf.h
@@ -0,0 +1,255 @@
+/*
+ * Copyright (C) 2016 Cavium, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ */
+
+#ifndef __CPTVF_H
+#define __CPTVF_H
+
+#include 
+#include "cpt_common.h"
+
+struct command_chunk {
+   uint8_t *head; /* 128-byte aligned real_vaddr */
+   uint8_t *real_vaddr; /* Virtual address after dma_alloc_consistent */
+   dma_addr_t dma_addr; /* 128-byte aligned real_dma_addr */
+   dma_addr_t real_dma_addr; /* DMA address after dma_alloc_consistent */
+   uint32_t size; /* Chunk size, max CPT_INST_CHUNK_MAX_SIZE */
+   struct hlist_node nextchunk;
+};
+
+struct iq_stats {
+   atomic64_t instr_posted;
+   atomic64_t instr_dropped;
+};
+
+/**
+ * comamnd queue structure
+ */
+struct command_queue {
+   spinlock_t lock; /* command queue lock */
+   uint32_t idx; /* Command queue host write idx */
+   uint32_t dbell_count; /* outstanding commands */
+   uint32_t nchunks; /* Number of command chunks */
+   struct command_chunk *qhead;/* Command queue head, instructions
+* are inserted here
+*/
+   struct hlist_head chead;
+   struct iq_stats stats; /* Queue statistics */
+};
+
+struct command_qinfo {
+   uint32_t dbell_thold; /* Command queue doorbell threshold */
+   uint32_t cmd_size; /* Command size (32/64-Byte) */
+   uint32_t qchunksize; /* Command queue chunk size configured by user */
+   struct command_queue queue[DEFAULT_DEVICE_QUEUES];
+};
+
+/**
+ * pending entry structure
+ */
+struct pending_entry {
+   uint8_t busy; /* Entry status (free/busy) */
+   uint8_t done;
+   uint8_t is_ae;
+
+   volatile uint64_t *completion_addr; /* Completion address */
+   void *post_arg;
+   void (*callback)(int, void *); /* Kernel ASYNC request callabck */
+   void *callback_arg; /* Kernel ASYNC request callabck arg */
+};
+
+/**
+ * pending queue structure
+ */
+struct pending_queue {
+   struct pending_entry *head; /* head of the queue */
+   uint32_t front; /* Process work from here */
+   uint32_t rear; /* Append new work here */
+   atomic64_t pending_count;
+   spinlock_t lock; /* Queue lock */
+};
+
+struct pending_qinfo {
+   uint32_t nr_queues; /* 

[PATCH 3/3] drivers: crypto: Enable CPT options crypto for build

[gcherianv]

From: George Cherian 

Add the CPT options in crypto Kconfig and update the
crypto Makefile

Signed-off-by: George Cherian 
---
 drivers/crypto/Kconfig  | 1 +
 drivers/crypto/Makefile | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 4d2b81f..15f9040 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -484,6 +484,7 @@ config CRYPTO_DEV_MXS_DCP
  will be called mxs-dcp.
 
 source "drivers/crypto/qat/Kconfig"
+source "drivers/crypto/cavium/cpt/Kconfig"
 
 config CRYPTO_DEV_QCE
tristate "Qualcomm crypto engine accelerator"
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index ad7250f..dd33290 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -32,3 +32,4 @@ obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
 obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/
 obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/
 obj-$(CONFIG_CRYPTO_DEV_CHELSIO) += chelsio/
+obj-$(CONFIG_CRYPTO_DEV_CPT) += cavium/cpt/
-- 
2.1.4

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Re: [patch] s390/crypto: unlock on error in prng_tdes_read()

[Martin Schwidefsky]

On Fri, 18 Nov 2016 14:11:00 +0300
Dan Carpenter  wrote:

> We added some new locking but forgot to unlock on error.
> 
> Fixes: 57127645d79d ("s390/zcrypt: Introduce new SHA-512 based Pseudo Random 
> Generator.")
> Signed-off-by: Dan Carpenter 
> 
> diff --git a/arch/s390/crypto/prng.c b/arch/s390/crypto/prng.c
> index 9cc050f..1113389 100644
> --- a/arch/s390/crypto/prng.c
> +++ b/arch/s390/crypto/prng.c
> @@ -507,8 +507,10 @@ static ssize_t prng_tdes_read(struct file *file, char 
> __user *ubuf,
>   prng_data->prngws.byte_counter += n;
>   prng_data->prngws.reseed_counter += n;
> 
> - if (copy_to_user(ubuf, prng_data->buf, chunk))
> - return -EFAULT;
> + if (copy_to_user(ubuf, prng_data->buf, chunk)) {
> + ret = -EFAULT;
> + break;
> + }
> 
>   nbytes -= chunk;
>   ret += chunk;
> 

Nice spotting, I will add this to my fixes tree. Thank you..

-- 
blue skies,
   Martin.

"Reality continues to ruin my life." - Calvin.

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[PATCH] crypto: CTR DRBG - advance output buffer pointer

[Stephan Mueller]

The CTR DRBG segments the number of random bytes to be generated into
128 byte blocks. The current code misses the advancement of the output
buffer pointer when the requestor asks for more than 128 bytes of data.
In this case, the next 128 byte block of random numbers is copied to
the beginning of the output buffer again. This implies that only the
first 128 bytes of the output buffer would ever be filled.

The patch adds the advancement of the buffer pointer to fill the entire
buffer.

Signed-off-by: Stephan Mueller 
---
 crypto/drbg.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/crypto/drbg.c b/crypto/drbg.c
index fb33f7d..9a95b61 100644
--- a/crypto/drbg.c
+++ b/crypto/drbg.c
@@ -1766,6 +1766,7 @@ static int drbg_kcapi_sym_ctr(struct drbg_state *drbg,
init_completion(>ctr_completion);
 
outlen -= cryptlen;
+   outbuf += cryptlen;
}
 
return 0;
-- 
2.7.4


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bug in blkcipher_walk code

[Stephan Mueller]

Hi Herbert,

Once in a while I seem to trigger a bug in the blkcipher_walk code which I 
cannot track down. This bug happens sporadically where I assume that it has 
something to do with the memory management in the slow path of blkcipher_walk.

I am using the CTR DRBG code that in turn uses the ctr-aes-aesni 
implementation. The bug only appears when I want to obtain a random number 
that is less than the CTR AES block size. In my particular case, I want 4 
bytes from the DRBG.

The bug happens in arch/x86/crypto/aesni-intel_glue.c:ctr_crypt_final() at the 
line:

memcpy(dst, keystream, nbytes);

The bug looks like the following:

[   12.328676] BUG: unable to handle kernel paging request at a17ae418b988
[   12.328680] IP: [] ctr_crypt+0x19a/0x1c0
[   12.328681] PGD 66fed067
[   12.328681] PUD 0
[   12.328681]
[   12.328683] Oops: 0002 [#1] SMP
[   12.328692] Modules linked in: bridge(+) stp llc ebtable_nat ip6table_raw 
ip6table_security ip6table_mangle iptable_raw iptable_security iptable_mangle 
ebtable_filter ebtables ip6table_filter ip6_tables crct10dif_pclmul 
crc32_pclmul ghash_clmulni_intel pcspkr i2c_piix4 virtio_net virtio_balloon 
acpi_cpufreq sch_fq_codel virtio_console virtio_blk virtio_pci virtio_ring 
serio_raw crc32c_intel virtio
[   12.328693] CPU: 0 PID: 521 Comm: modprobe Not tainted 4.9.0-rc1+ #253
[   12.328694] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 
1.9.1-1.fc24 04/01/2014
[   12.328694] task: a17ab8453fc0 task.stack: bdafc0744000
[   12.328696] RIP: 0010:[]  [] ctr_crypt
+0x19a/0x1c0
[   12.328696] RSP: 0018:bdafc0747a60  EFLAGS: 00010002
[   12.328697] RAX: 32e455a6 RBX: 0004 RCX: 
0002
[   12.328697] RDX: 0001 RSI: 0086 RDI: 
0086
[   12.328698] RBP: bdafc0747b28 R08: a17abc16e900 R09: 
0019
[   12.328698] R10: a17a764f68b0 R11: 0002e918 R12: 
bdafc0747b38
[   12.328698] R13: a17a764f6840 R14: a17ae418b988 R15: 
bdafc0747a70
[   12.328699] FS:  7f55f57a6700() GS:a17abfc0() knlGS:

[   12.328700] CS:  0010 DS:  ES:  CR0: 80050033
[   12.328700] CR2: a17ae418b988 CR3: 79b26000 CR4: 
003406f0
[   12.328703] Stack:
[   12.328705]  a17abc16e900 a17ab845fd80 2ae7e40732e455a6 
3a224612a8f9841d
[   12.328706]  fb4e81e117c0 a17ab845fd80 fb4e829062c0 
a17ae418b988
[   12.328707]  bdafc0747ba8 0d80 0004 
bdafc0747bc8
[   12.328708] Call Trace:
[   12.328712]  [] __ablk_encrypt+0x43/0x50
[   12.328714]  [] ablk_encrypt+0x32/0xc0
[   12.328716]  [] skcipher_encrypt_ablkcipher+0x5e/0x60
[   12.328717]  [] drbg_kcapi_sym_ctr+0xb0/0x130
[   12.328719]  [] drbg_ctr_generate+0x53/0x80


Now, the interesting part is the following: the original memory pointer that 
shall be processed by the DRBG is in my example c018b988 -- this 
pointer is used until the DRBG invokes crypto_skcipher_encrypt. However, when 
I print out the buffer pointer that is used as dst in the memcpy of 
ctr_crypt_final, I see a17ae418b988 -- i.e. the buffer that causes paging 
failure.

During tracing the blkcipher_walk code I see that the slow code path is used 
when the request size is smaller than the block size. That slow code path 
allocates new memory that will be used for the dst pointer in ctr_crypt_final.

May I ask you for checking whether the allocation and the memory pointer logic 
has an issue that would cause a paging failure?

Ciao
Stephan
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[patch] s390/crypto: unlock on error in prng_tdes_read()

[Dan Carpenter]

We added some new locking but forgot to unlock on error.

Fixes: 57127645d79d ("s390/zcrypt: Introduce new SHA-512 based Pseudo Random 
Generator.")
Signed-off-by: Dan Carpenter 

diff --git a/arch/s390/crypto/prng.c b/arch/s390/crypto/prng.c
index 9cc050f..1113389 100644
--- a/arch/s390/crypto/prng.c
+++ b/arch/s390/crypto/prng.c
@@ -507,8 +507,10 @@ static ssize_t prng_tdes_read(struct file *file, char 
__user *ubuf,
prng_data->prngws.byte_counter += n;
prng_data->prngws.reseed_counter += n;
 
-   if (copy_to_user(ubuf, prng_data->buf, chunk))
-   return -EFAULT;
+   if (copy_to_user(ubuf, prng_data->buf, chunk)) {
+   ret = -EFAULT;
+   break;
+   }
 
nbytes -= chunk;
ret += chunk;
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[PATCH net-next] cxgb4: Allocate Tx queues dynamically

[Atul Gupta]

From: Hariprasad Shenai 

Allocate resources dynamically for Upper layer driver's (ULD) like
cxgbit, iw_cxgb4, cxgb4i and chcr. The resources allocated include Tx
queues which are allocated when ULD register with cxgb4 driver and freed
while un-registering. The Tx queues which are shared by ULD shall be
allocated by first registering driver and un-allocated by last
unregistering driver.

Signed-off-by: Atul Gupta 
---
 drivers/crypto/chelsio/chcr_algo.c |  16 +--
 drivers/crypto/chelsio/chcr_core.c |   3 +-
 drivers/infiniband/hw/cxgb4/device.c   |   1 +
 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h |  19 +++-
 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c |  12 --
 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c|  64 +++
 drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.c | 114 +++
 drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.h |  17 +++
 drivers/net/ethernet/chelsio/cxgb4/sge.c   | 121 +++--
 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c |   1 +
 drivers/target/iscsi/cxgbit/cxgbit_main.c  |   1 +
 11 files changed, 287 insertions(+), 82 deletions(-)

diff --git a/drivers/crypto/chelsio/chcr_algo.c 
b/drivers/crypto/chelsio/chcr_algo.c
index e4ddb921d7b3..56b153805462 100644
--- a/drivers/crypto/chelsio/chcr_algo.c
+++ b/drivers/crypto/chelsio/chcr_algo.c
@@ -592,16 +592,18 @@ static int chcr_aes_cbc_setkey(struct crypto_ablkcipher 
*tfm, const u8 *key,
 
 static int cxgb4_is_crypto_q_full(struct net_device *dev, unsigned int idx)
 {
-   int ret = 0;
-   struct sge_ofld_txq *q;
struct adapter *adap = netdev2adap(dev);
+   struct sge_uld_txq_info *txq_info =
+   adap->sge.uld_txq_info[CXGB4_TX_CRYPTO];
+   struct sge_uld_txq *txq;
+   int ret = 0;
 
local_bh_disable();
-   q = >sge.ofldtxq[idx];
-   spin_lock(>sendq.lock);
-   if (q->full)
+   txq = _info->uldtxq[idx];
+   spin_lock(>sendq.lock);
+   if (txq->full)
ret = -1;
-   spin_unlock(>sendq.lock);
+   spin_unlock(>sendq.lock);
local_bh_enable();
return ret;
 }
@@ -674,11 +676,11 @@ static int chcr_device_init(struct chcr_context *ctx)
}
u_ctx = ULD_CTX(ctx);
rxq_perchan = u_ctx->lldi.nrxq / u_ctx->lldi.nchan;
-   ctx->dev->tx_channel_id = 0;
rxq_idx = ctx->dev->tx_channel_id * rxq_perchan;
rxq_idx += id % rxq_perchan;
spin_lock(>dev->lock_chcr_dev);
ctx->tx_channel_id = rxq_idx;
+   ctx->dev->tx_channel_id = !ctx->dev->tx_channel_id;
spin_unlock(>dev->lock_chcr_dev);
}
 out:
diff --git a/drivers/crypto/chelsio/chcr_core.c 
b/drivers/crypto/chelsio/chcr_core.c
index fb5f9bbfa09c..4d7f6700fd7e 100644
--- a/drivers/crypto/chelsio/chcr_core.c
+++ b/drivers/crypto/chelsio/chcr_core.c
@@ -42,6 +42,7 @@ static chcr_handler_func work_handlers[NUM_CPL_CMDS] = {
 static struct cxgb4_uld_info chcr_uld_info = {
.name = DRV_MODULE_NAME,
.nrxq = MAX_ULD_QSETS,
+   .ntxq = MAX_ULD_QSETS,
.rxq_size = 1024,
.add = chcr_uld_add,
.state_change = chcr_uld_state_change,
@@ -126,7 +127,7 @@ static int cpl_fw6_pld_handler(struct chcr_dev *dev,
 
 int chcr_send_wr(struct sk_buff *skb)
 {
-   return cxgb4_ofld_send(skb->dev, skb);
+   return cxgb4_crypto_send(skb->dev, skb);
 }
 
 static void *chcr_uld_add(const struct cxgb4_lld_info *lld)
diff --git a/drivers/infiniband/hw/cxgb4/device.c 
b/drivers/infiniband/hw/cxgb4/device.c
index 93e3d270a98a..4e5baf4fe15e 100644
--- a/drivers/infiniband/hw/cxgb4/device.c
+++ b/drivers/infiniband/hw/cxgb4/device.c
@@ -1481,6 +1481,7 @@ static int c4iw_uld_control(void *handle, enum 
cxgb4_control control, ...)
 static struct cxgb4_uld_info c4iw_uld_info = {
.name = DRV_NAME,
.nrxq = MAX_ULD_QSETS,
+   .ntxq = MAX_ULD_QSETS,
.rxq_size = 511,
.ciq = true,
.lro = false,
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h 
b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
index 2125903043fb..0bce1bf9ca0f 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
@@ -635,6 +635,7 @@ struct tx_sw_desc;
 
 struct sge_txq {
unsigned int  in_use;   /* # of in-use Tx descriptors */
+   unsigned int  q_type;   /* Q type Eth/Ctrl/Ofld */
unsigned int  size; /* # of descriptors */
unsigned int  cidx; /* SW consumer index */
unsigned int  pidx; /* producer index */
@@ -665,7 +666,7 @@ struct sge_eth_txq {/* state for an SGE 
Ethernet Tx queue */
unsigned long mapping_err;  /* # of I/O MMU packet mapping errors */
 } cacheline_aligned_in_smp;
 
-struct sge_ofld_txq {