On 17 February 2015 at 04:09, George Spelvin wrote:
> I discovered when (belatedly) testing 3.19-rc7 the other week that
> my laptop wifi was broken and would no longer associate.
>
> Apparently this is causing some necessary crypto algorithms to fail to
> load, breaking my wifi.
>
> Perhaps I'm d
I discovered when (belatedly) testing 3.19-rc7 the other week that
my laptop wifi was broken and would no longer associate.
I wasted a lot of time trying to bisect changes in net/wireless and
net/drivers wireless before figuring out that it was sonewhere else in
the kernel. An unrestricted bisect
Hi,
This patchset prepares the driver to be built on non-MIPS bcm63xx architectures
such as the ARM bcm63xx variants, thanks!
Although patch 3 touches a MIPS header file, there should be little to no
conflicts there if all patches went through the hw_random tree (is there one?)
Thanks!
Florian
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h contains the register
definitions for this random number generator block, incorporate these
register definitions directly into the bcm63xx-rng driver so we do not
rely on this header to be provided.
Signed-off-by: Florian Fainelli
---
drivers/cha
Simplify the driver's probe function and error handling by using the
device managed allocators, while at it, drop the redundant "out of
memory" messages since these are already printed by the allocator.
Signed-off-by: Florian Fainelli
---
drivers/char/hw_random/bcm63xx-rng.c | 20 ++-
Now that these definitions have been moved to
drivers/char/hw_random/bcm63xx-rng.c where they belong to make the
driver standalone, we can safely remove these definitions from
bcm63xx_regs.h.
Signed-off-by: Florian Fainelli
---
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 14 -
bcm_{readl,writel} macros expand to __raw_{readl,writel}, use these
directly such that we do not rely on the platform to provide these for
us. As a result, we no longer use bcm63xx_io.h, so remove that inclusion
too.
Signed-off-by: Florian Fainelli
---
drivers/char/hw_random/bcm63xx-rng.c | 13 +
* Sebastian Andrzej Siewior | 2015-02-16 12:18:22 [+0100]:
>Known issues:
>
> - xor / raid_pq
>I had max latency jumping up to 67563us on one CPU while the next
>lower max was 58us. I tracked it down to module's init code of
>xor and raid_pq. Both disable preemption wh
> Von: linux-crypto-ow...@vger.kernel.org
> [linux-crypto-ow...@vger.kernel.org]" im Auftrag von "Segher
> Boessenkool [seg...@kernel.crashing.org]
> Gesendet: Montag, 16. Februar 2015 15:37
> An: David Laight
> Cc: Markus Stockhausen; linux-crypto@vger.kernel.org;
> linuxppc-...@lists.ozlabs.or
From: Markus Stockhausen
> 4K AES tables for big endian
I can't help feeling that you could give more information about how the
values are generated.
...
> + * These big endian AES encryption/decryption tables are designed to be
> simply
> + * accessed by a combination of rlwimi/lwz instruction
On Mon, Feb 16, 2015 at 02:19:50PM +, David Laight wrote:
> From: Markus Stockhausen
> > 4K AES tables for big endian
>
> I can't help feeling that you could give more information about how the
> values are generated.
... and an explanation of why this does not open you up to a timing attack
[PATCH v1 3/7] AES for PPC/SPE - assembler core
The assembler AES encryption and decryption core routines.
Implemented & optimized for big endian. Nevertheless they
work on little endian too.
For most efficient reuse in (higher level) block cipher
routines they are implemented as "fast" call mod
[PATCH v1 5/7] AES for PPC/SPE - ECB/CBC/CTR/XTS modes
The assembler block cipher module that controls the core
AES functions.
Signed-off-by: Markus Stockhausen
diff --git a/arch/powerpc/crypto/aes-spe-modes.S
b/arch/powerpc/crypto/aes-spe-modes.S
new file mode 100644
index 000..1141841
--
[PATCH v1 2/7] AES for PPC/SPE - aes tables
4K AES tables for big endian
Signed-off-by: Markus Stockhausen
diff --git a/arch/powerpc/crypto/aes-tab-4k.S b/arch/powerpc/crypto/aes-tab-4k.S
new file mode 100644
index 000..6bc1755
--- /dev/null
+++ b/arch/powerpc/crypto/aes-tab-4k.S
@@ -0,0 +1
[PATCH v1 0/7] AES for PPC/SPE
The following patches add support for 64bit accelerated AES
calculation on PPC processors with SPE instruction set. Besides
the AES core module it implements ECB/CBC/CTR/XTS as block
ciphers. The implementation takes care of the following
constraints:
- save SPE re
[PATCH v1 7/7] AES for PPC/SPE - kernel config
Integrate the module into the kernel configuration
Signed-off-by: Markus Stockhausen
diff --git a/arch/powerpc/crypto/Makefile b/arch/powerpc/crypto/Makefile
index a07e763..1698fb9 100644
--- a/arch/powerpc/crypto/Makefile
+++ b/arch/powerpc/crypto
[PATCH v1 4/7] AES for PPC/SPE - key handling
Key generation for big endian core routines.
Signed-off-by: Markus Stockhausen
diff --git a/arch/powerpc/crypto/aes-spe-keys.S
b/arch/powerpc/crypto/aes-spe-keys.S
new file mode 100644
index 000..55b258c
--- /dev/null
+++ b/arch/powerpc/crypto/
[PATCH v1 1/7] AES for PPC/SPE - register defines
Define some register aliases for better readability.
Signed-off-by: Markus Stockhausen
diff --git a/arch/powerpc/crypto/aes-spe-regs.h
b/arch/powerpc/crypto/aes-spe-regs.h
new file mode 100644
index 000..30d217b
--- /dev/null
+++ b/arch/pow
[PATCH v1 6/7] AES for PPC/SPE - glue code
Integrate the assembler modules into the kernel crypto
framework. Take care to avoid long intervals of disabled
preemption.
Signed-off-by: Markus Stockhausen
diff --git a/arch/powerpc/crypto/aes_spe_glue.c
b/arch/powerpc/crypto/aes_spe_glue.c
new file
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