Re: [PATCH 3/3] drivers: crypto: Enable CPT options crypto for build

Hi George, [auto build test ERROR on cryptodev/master] [also build test ERROR on v4.9-rc5 next-20161117] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url:

Re: [PATCH 1/3] drivers: crypto: Add Support for Octeon-tx CPT Engine

Hi David, Thanks for the review. On Saturday 19 November 2016 12:25 AM, David Daney wrote: On 11/18/2016 07:00 AM, gcheri...@gmail.com wrote: From: George Cherian Enable the Physical Function diver for the Cavium Crypto Engine (CPT) found in Octeon-tx series of

Re: [PATCH 1/3] drivers: crypto: Add Support for Octeon-tx CPT Engine

On 11/18/2016 07:00 AM, gcheri...@gmail.com wrote: From: George Cherian Enable the Physical Function diver for the Cavium Crypto Engine (CPT) found in Octeon-tx series of SoC's. CPT is the Cryptographic Acceleration Unit. CPT includes microcoded GigaCypher symmetric

Re: [PATCH net-next] cxgb4: Allocate Tx queues dynamically

From: Atul Gupta Date: Fri, 18 Nov 2016 16:37:40 +0530 > From: Hariprasad Shenai > > Allocate resources dynamically for Upper layer driver's (ULD) like > cxgbit, iw_cxgb4, cxgb4i and chcr. The resources allocated include Tx > queues which are

[PATCH] hw_random: Make explicit that max >= 32 always

As hw_random core calls ->read with max > 32 or more, make it explicit. Also remove checks involving 'max' being less than 8. Signed-off-by: PrasannaKumar Muralidharan --- drivers/char/hw_random/msm-rng.c | 4 drivers/char/hw_random/pic32-rng.c | 3 ---

[PATCH 1/3] drivers: crypto: Add Support for Octeon-tx CPT Engine

From: George Cherian Enable the Physical Function diver for the Cavium Crypto Engine (CPT) found in Octeon-tx series of SoC's. CPT is the Cryptographic Acceleration Unit. CPT includes microcoded GigaCypher symmetric engines (SEs) and asymmetric engines (AEs).

[PATCH 2/3] drivers: crypto: Add the Virtual Function driver for CPT

From: George Cherian Enable the CPT VF driver. CPT is the cryptographic Accelaration Unit in Octeon-tx series of processors. Signed-off-by: George Cherian --- drivers/crypto/cavium/cpt/Kconfig| 10 +

[PATCH 3/3] drivers: crypto: Enable CPT options crypto for build

From: George Cherian Add the CPT options in crypto Kconfig and update the crypto Makefile Signed-off-by: George Cherian --- drivers/crypto/Kconfig | 1 + drivers/crypto/Makefile | 1 + 2 files changed, 2 insertions(+) diff --git

Re: [patch] s390/crypto: unlock on error in prng_tdes_read()

On Fri, 18 Nov 2016 14:11:00 +0300 Dan Carpenter wrote: > We added some new locking but forgot to unlock on error. > > Fixes: 57127645d79d ("s390/zcrypt: Introduce new SHA-512 based Pseudo Random > Generator.") > Signed-off-by: Dan Carpenter

[PATCH] crypto: CTR DRBG - advance output buffer pointer

The CTR DRBG segments the number of random bytes to be generated into 128 byte blocks. The current code misses the advancement of the output buffer pointer when the requestor asks for more than 128 bytes of data. In this case, the next 128 byte block of random numbers is copied to the beginning of

bug in blkcipher_walk code

Hi Herbert, Once in a while I seem to trigger a bug in the blkcipher_walk code which I cannot track down. This bug happens sporadically where I assume that it has something to do with the memory management in the slow path of blkcipher_walk. I am using the CTR DRBG code that in turn uses the

[patch] s390/crypto: unlock on error in prng_tdes_read()

We added some new locking but forgot to unlock on error. Fixes: 57127645d79d ("s390/zcrypt: Introduce new SHA-512 based Pseudo Random Generator.") Signed-off-by: Dan Carpenter diff --git a/arch/s390/crypto/prng.c b/arch/s390/crypto/prng.c index 9cc050f..1113389 100644

[PATCH net-next] cxgb4: Allocate Tx queues dynamically

From: Hariprasad Shenai Allocate resources dynamically for Upper layer driver's (ULD) like cxgbit, iw_cxgb4, cxgb4i and chcr. The resources allocated include Tx queues which are allocated when ULD register with cxgb4 driver and freed while un-registering. The Tx queues