Re: [RFC PATCH v4] IV Generation algorithms for dm-crypt

On Tue, Feb 7, 2017 at 12:35 PM, Binoy Jayan wrote: > === > dm-crypt optimization for larger block sizes > === > >

Re: [PATCH v2 2/5] async_tx: Handle DMA devices having support for fewer PQ coefficients

On Tue, Feb 7, 2017 at 10:12 PM, Vinod Koul wrote: > On Tue, Feb 07, 2017 at 02:32:15PM +0530, Anup Patel wrote: >> On Tue, Feb 7, 2017 at 1:57 PM, Dan Williams >> wrote: >> > On Tue, Feb 7, 2017 at 12:16 AM, Anup Patel

[PATCH] Revert "hwrng: core - zeroize buffers with random data"

This reverts commit 2cc751545854d7bd7eedf4d7e377bb52e176cd07. With this commit in place I get on a Cavium ThunderX (arm64) system: $ if=/dev/hwrng bs=256 count=1 | od -t x1 -A x -v > rng-bad.txt 1+0 records in 1+0 records out 256 bytes (256 B) copied, 9.1171e-05 s, 2.8 MB/s $ dd if=/dev/hwrng

Re: [PATCH v2 2/5] async_tx: Handle DMA devices having support for fewer PQ coefficients

On Tue, Feb 7, 2017 at 1:02 AM, Anup Patel wrote: > On Tue, Feb 7, 2017 at 1:57 PM, Dan Williams wrote: >> On Tue, Feb 7, 2017 at 12:16 AM, Anup Patel wrote: >>> The DMAENGINE framework assumes that if PQ offload is

Re: [bug report] crypto: atmel-sha - update request queue management to make it more generic

Hi Dan, Le 07/02/2017 à 11:56, Dan Carpenter a écrit : > Hello Cyrille Pitchen, > > The patch a29af939b24d: "crypto: atmel-sha - update request queue > management to make it more generic" from Jan 26, 2017, leads to the > following static checker warning: > >

Re: [PATCH v2 2/5] async_tx: Handle DMA devices having support for fewer PQ coefficients

On Tue, Feb 07, 2017 at 02:32:15PM +0530, Anup Patel wrote: > On Tue, Feb 7, 2017 at 1:57 PM, Dan Williams wrote: > > On Tue, Feb 7, 2017 at 12:16 AM, Anup Patel wrote: > >> The DMAENGINE framework assumes that if PQ offload is supported by a >

[PATCH v6 3/3] drivers: crypto: Enable CPT options crypto for build

Add the CPT options in crypto Kconfig and update the crypto Makefile Update the MAINTAINERS file too. Signed-off-by: George Cherian Reviewed-by: David Daney --- MAINTAINERS | 7 +++ drivers/crypto/Kconfig | 1 +

[PATCH v6 1/3] drivers: crypto: Add Support for Octeon-tx CPT Engine

Enable the Physical Function driver for the Cavium Crypto Engine (CPT) found in Octeon-tx series of SoC's. CPT is the Cryptographic Accelaration Unit. CPT includes microcoded GigaCypher symmetric engines (SEs) and asymmetric engines (AEs). Signed-off-by: George Cherian

[PATCH v6 2/3] drivers: crypto: Add the Virtual Function driver for CPT

Enable the CPT VF driver. CPT is the cryptographic Acceleration Unit in Octeon-tx series of processors. Signed-off-by: George Cherian Reviewed-by: David Daney --- drivers/crypto/cavium/cpt/Makefile | 3 +-

[PATCH v6 0/3] Add Support for Cavium Cryptographic Acceleration Unit

This series adds the support for Cavium Cryptographic Accelerarion Unit (CPT) CPT is available in Cavium's Octeon-Tx SoC series. The series was tested with ecryptfs and dm-crypt for in

[PATCH] crypto: atmel-sha: use %zu for size_t print format specifier

From: Colin Ian King The size_t types should be using %zu as a format specifier rather than %d and %u. Signed-off-by: Colin Ian King --- drivers/crypto/atmel-sha.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff

[bug report] crypto: atmel-sha - update request queue management to make it more generic

Hello Cyrille Pitchen, The patch a29af939b24d: "crypto: atmel-sha - update request queue management to make it more generic" from Jan 26, 2017, leads to the following static checker warning: drivers/crypto/atmel-sha.c:673 atmel_sha_xmit_dma() error: we previously assumed

[RFC PATCH v4] crypto: Add IV generation algorithms

Currently, the iv generation algorithms are implemented in dm-crypt.c. The goal is to move these algorithms from the dm layer to the kernel crypto layer by implementing them as template ciphers so they can be implemented in hardware for performance. As part of this patchset, the iv-generation code

[RFC PATCH v4] IV Generation algorithms for dm-crypt

=== dm-crypt optimization for larger block sizes === Currently, the iv generation algorithms are implemented in dm-crypt.c. The goal is to move

Re: [PATCH v2 2/5] async_tx: Handle DMA devices having support for fewer PQ coefficients

On Tue, Feb 7, 2017 at 1:57 PM, Dan Williams wrote: > On Tue, Feb 7, 2017 at 12:16 AM, Anup Patel wrote: >> The DMAENGINE framework assumes that if PQ offload is supported by a >> DMA device then all 256 PQ coefficients are supported. This

Re: [PATCH v2 2/5] async_tx: Handle DMA devices having support for fewer PQ coefficients

On Tue, Feb 7, 2017 at 12:16 AM, Anup Patel wrote: > The DMAENGINE framework assumes that if PQ offload is supported by a > DMA device then all 256 PQ coefficients are supported. This assumption > does not hold anymore because we now have BCM-SBA-RAID offload engine >

[PATCH v2 2/5] async_tx: Handle DMA devices having support for fewer PQ coefficients

The DMAENGINE framework assumes that if PQ offload is supported by a DMA device then all 256 PQ coefficients are supported. This assumption does not hold anymore because we now have BCM-SBA-RAID offload engine which supports PQ offload with limited number of PQ coefficients. This patch extends

[PATCH v2 5/5] dt-bindings: Add DT bindings document for Broadcom SBA RAID driver

This patch adds the DT bindings document for newly added Broadcom SBA RAID driver. Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- .../devicetree/bindings/dma/brcm,iproc-sba.txt | 29

[PATCH v2 4/5] dmaengine: Add Broadcom SBA RAID driver

The Broadcom stream buffer accelerator (SBA) provides offloading capabilities for RAID operations. This SBA offload engine is accessible via Broadcom SoC specific ring manager. This patch adds Broadcom SBA RAID driver which provides one DMA device with RAID capabilities using one or more Broadcom

[PATCH v2 3/5] async_tx: Fix DMA_PREP_FENCE usage in do_async_gen_syndrome()

The DMA_PREP_FENCE is to be used when preparing Tx descriptor if output of Tx descriptor is to be used by next/dependent Tx descriptor. The DMA_PREP_FENSE will not be set correctly in do_async_gen_syndrome() when calling dma->device_prep_dma_pq() under following conditions: 1. ASYNC_TX_FENCE not

[PATCH v2 1/5] lib/raid6: Add log-of-2 table for RAID6 HW requiring disk position

The raid6_gfexp table represents {2}^n values for 0 <= n < 256. The Linux async_tx framework pass values from raid6_gfexp as coefficients for each source to prep_dma_pq() callback of DMA channel with PQ capability. This creates problem for RAID6 offload engines (such as Broadcom SBA) which take

[PATCH v2 0/5] Broadcom SBA RAID support

The Broadcom SBA RAID is a stream-based device which provides RAID5/6 offload. It requires a SoC specific ring manager (such as Broadcom FlexRM ring manager) to provide ring-based programming interface. Due to this, the Broadcom SBA RAID driver (mailbox client) implements DMA device having one