Re: [PATCH v3 1/3] clk: meson-gxbb: expose clock CLKID_RNG0

Quoting Kevin Hilman (2017-03-22 08:24:08) > Herbert Xu writes: > > > On Thu, Mar 16, 2017 at 11:24:31AM -0700, Kevin Hilman wrote: > >> Hi Herbert, > >> > >> Herbert Xu writes: > >> > >> > On Wed, Feb 22, 2017 at 07:55:24AM +0100,

race condition in kernel/padata.c

Hey Steffen, WireGuard makes really heavy use of padata, feeding it units of work from different cores in different contexts all at the same time. For the most part, everything has been fine, but one particular user has consistently run into mysterious bugs. He's using a rather old dual core CPU,

Re: [PATCH v3 1/3] clk: meson-gxbb: expose clock CLKID_RNG0

Herbert Xu writes: > On Thu, Mar 16, 2017 at 11:24:31AM -0700, Kevin Hilman wrote: >> Hi Herbert, >> >> Herbert Xu writes: >> >> > On Wed, Feb 22, 2017 at 07:55:24AM +0100, Heiner Kallweit wrote: >> >> Expose clock CLKID_RNG0 which is

[PATCH] crypto: DRBG - initialize SGL only once

An SGL to be initialized only once even when its buffers are written to several times. Signed-off-by: Stephan Mueller --- crypto/drbg.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/crypto/drbg.c b/crypto/drbg.c index 8a4d98b..fa749f4 100644 ---

[PATCH] arm64: dts: ls1012a: add crypto node

LS1012A has a SEC v5.4 security engine. Signed-off-by: Horia Geantă --- arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 9 +++ arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 9 +++ arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 9 +++