[PATCH] crypto: sha512-mb - remove HASH_FIRST flag

From: Eric Biggers The HASH_FIRST flag is never set. Remove it. Signed-off-by: Eric Biggers --- arch/x86/crypto/sha512-mb/sha512_mb.c | 30 +++--- arch/x86/crypto/sha512-mb/sha512_mb_ctx.h | 8 +++- 2 files changed, 6

[PATCH] crypto: sha1-mb - remove HASH_FIRST flag

From: Eric Biggers The HASH_FIRST flag is never set. Remove it. Signed-off-by: Eric Biggers --- arch/x86/crypto/sha1-mb/sha1_mb.c | 28 +++- arch/x86/crypto/sha1-mb/sha1_mb_ctx.h | 8 +++- 2 files changed, 6

[PATCH] crypto: mcryptd - remove pointless wrapper functions

From: Eric Biggers There is no need for ahash_mcryptd_{update,final,finup,digest}(); we should just call crypto_ahash_*() directly. Signed-off-by: Eric Biggers --- crypto/mcryptd.c | 34 --

[PATCH] crypto: sha256-mb - remove HASH_FIRST flag

From: Eric Biggers The HASH_FIRST flag is never set. Remove it. Signed-off-by: Eric Biggers --- arch/x86/crypto/sha256-mb/sha256_mb.c | 27 +++ arch/x86/crypto/sha256-mb/sha256_mb_ctx.h | 8 +++- 2 files changed, 6

Re: [RESEND PATCH 3/6] ARM: dts: imx7s: add CAAM device node

On 24/01/18 22:48, Bryan O'Donoghue wrote: The clock configuration has changed to just one CAAM-specific clock in addition to the ahb clock. This also means that additional modifications to the CAAM driver are necessary or it will complain that it doesn't find all clocks. Sure - but, those

Re: [RESEND PATCH 3/6] ARM: dts: imx7s: add CAAM device node

On 24/01/18 18:12, Auer, Lukas wrote: On Wed, 2018-01-24 at 14:50 +, Bryan O'Donoghue wrote: From: Rui Miguel Silva Add CAAM device node to the i.MX7s device tree. Signed-off-by: Rui Miguel Silva Cc: "Horia Geantă" Cc:

Re: [PATCH] sparc64: fix typo in CONFIG_CRYPTO_DES_SPARC64 => CONFIG_CRYPTO_CAMELLIA_SPARC64

From: Corentin Labbe Date: Tue, 23 Jan 2018 14:33:14 + > This patch fixes the typo CONFIG_CRYPTO_DES_SPARC64 => > CONFIG_CRYPTO_CAMELLIA_SPARC64 > > Fixes: 81658ad0d923 ("sparc64: Add CAMELLIA driver making use of the new > camellia opcodes.") > Signed-off-by:

Re: [RESEND PATCH 3/6] ARM: dts: imx7s: add CAAM device node

On Wed, 2018-01-24 at 14:50 +, Bryan O'Donoghue wrote: > From: Rui Miguel Silva > > Add CAAM device node to the i.MX7s device tree. > > Signed-off-by: Rui Miguel Silva > Cc: "Horia Geantă" > Cc: Aymen Sghaier

Re: [PATCH 3/3] arm64: enable 128-bit memory read/write support

On Wed, Jan 24, 2018 at 02:00:42PM +0100, Geert Uytterhoeven wrote: > Hi Yury, > > On Wed, Jan 24, 2018 at 10:05 AM, Yury Norov > wrote: > > Introduce __raw_writeo(), __raw_reado() and other arch-specific > > RW functions for 128-bit memory access, and enable it for

Re: [PATCH RFC 0/3] API for 128-bit IO access

On Wed, Jan 24, 2018 at 4:05 AM, Yury Norov wrote: > > ... > With all that, this example code: > > static int __init 128bit_test(void) > { > __uint128_t v; > __uint128_t addr; > __uint128_t val = (__uint128_t) 0x1234567890abc; > ... In case it

Re: [PATCH RFC 0/3] API for 128-bit IO access

On Wed, Jan 24, 2018 at 12:28 PM, Arnd Bergmann wrote: > On Wed, Jan 24, 2018 at 10:05 AM, Yury Norov > wrote: >> * For 128-bit read/write functions I take suffix 'o', which means read/write >> the octet of bytes. Is this name OK? > > Can't think of

Re: Odroid HC1 cryptsetup:encrypt sata driver

Hi Krzysztof, On 24 January 2018 at 19:31, Krzysztof Kozlowski wrote: > On Wed, Jan 24, 2018 at 2:04 PM, Anand Moon wrote: >> Hi Kamil Konieczny, >> >> I am looking in setup of encrypted sata hard-disk on Odroid XU4/HC1 device. >> using following

[RESEND PATCH 1/6] crypto: caam: Fix null dereference at error path

From: Rui Miguel Silva caam_remove already removes the debugfs entry, so we need to remove the one immediately before calling caam_remove. This fix a NULL dereference at error paths is caam_probe fail. [bod: changed name prefix to "crypto: caam: Fix .."] [bod: added Fixes

[RESEND PATCH 3/6] ARM: dts: imx7s: add CAAM device node

From: Rui Miguel Silva Add CAAM device node to the i.MX7s device tree. Signed-off-by: Rui Miguel Silva Cc: "Horia Geantă" Cc: Aymen Sghaier Cc: Fabio Estevam Cc: Peng Fan

[RESEND PATCH 4/6] imx7d: add CAAM clocks

From: Rui Miguel Silva Add CAAM clocks so that we could use the Cryptographic Acceleration and Assurance Module (CAAM) hardware block. Signed-off-by: Rui Miguel Silva Cc: "Horia Geantă" Cc: Aymen Sghaier

[RESEND PATCH 5/6] crypto: caam: add logic to detect when running under TrustZone

This patch introduces logic to ascertain if the CAAM is running in TrustZone mode or not. When running in TrustZone mode the first page of the CAAM will read-back all zero for each register. This means for a register such as the MCR - if we detect an all zero register - we can run a simple test to

[RESEND PATCH 6/6] crypto: caam: detect RNG init when TrustZone is active

When TrustZone is enabled on sec4 compatible silicon the first page of the CAAM is reserved for TrustZone only, this means that access to the deco registers is restricted and will return zero when read. The solution to this problem is to initialize the RNG prior to TrustZone being enabled or to

[RESEND PATCH 2/6] crypto: caam: Fix endless loop when RNG is already initialized

commit 1005bccd7a4a ("crypto: caam - enable instantiation of all RNG4 state handles") introduces a control when incrementing ent_delay which contains the following comment above it: /* * If either SH were instantiated by somebody else * (e.g. u-boot) then it is assumed that the entropy *

[RESEND PATCH 0/6] Enable CAAM on i.MX7s fix TrustZone issues

This patch-set enables CAAM on the i.MX7s and fixes a number of issues identified with the CAAM driver and hardware when TrustZone mode is enabled. The first block of patches are simple bug-fixes, followed by a second block of patches which are simple enabling patches for the i.MX7Solo - note we

Re: [PATCH 0/6] Enable CAAM on i.MX7s fix TrustZone issues

crap - looks like just the cover note got sent. sorry folks

[PATCH 0/6] Enable CAAM on i.MX7s fix TrustZone issues

This patch-set enables CAAM on the i.MX7s and fixes a number of issues identified with the CAAM driver and hardware when TrustZone mode is enabled. The first block of patches are simple bug-fixes, followed by a second block of patches which are simple enabling patches for the i.MX7Solo - note we

Re: Odroid HC1 cryptsetup:encrypt sata driver

On Wed, Jan 24, 2018 at 2:04 PM, Anand Moon wrote: > Hi Kamil Konieczny, > > I am looking in setup of encrypted sata hard-disk on Odroid XU4/HC1 device. > using following encryption method. > > aes-cbc-essiv:sha256 128 > aes-cbc-essiv:sha256 256 > > Here is my defconfig I

Re: [PATCH] crypto: picoxcell - Fix error handling in spacc_probe()

Thanks Alexey! On Sat, Jan 20, 2018 at 12:53:15AM +0300, Alexey Khoroshilov wrote: > If clk_get() fails, device_remove_file() looks inappropriate. > > The error path, where all crypto_register fail, misses resource > deallocations. > > Found by Linux Driver Verification project

Odroid HC1 cryptsetup:encrypt sata driver

Hi Kamil Konieczny, I am looking in setup of encrypted sata hard-disk on Odroid XU4/HC1 device. using following encryption method. aes-cbc-essiv:sha256 128 aes-cbc-essiv:sha256 256 Here is my defconfig I am using. https://pastebin.com/gF5T2stp Following crypt benchmark we use to test :

Re: [PATCH 3/3] arm64: enable 128-bit memory read/write support

Hi Yury, On Wed, Jan 24, 2018 at 10:05 AM, Yury Norov wrote: > Introduce __raw_writeo(), __raw_reado() and other arch-specific > RW functions for 128-bit memory access, and enable it for arm64. > > 128-bit I/O is required for example by Octeon TX2 device to access >

Re: [PATCH RFC 0/3] API for 128-bit IO access

On Wed, Jan 24, 2018 at 10:05 AM, Yury Norov wrote: > This series adds API for 128-bit memory IO access and enables it for ARM64. > The original motivation for 128-bit API came from new Cavium network device > driver. The hardware requires 128-bit access to make things

Re: [PATCH RFC 0/3] API for 128-bit IO access

On Wed, Jan 24, 2018 at 12:05:16PM +0300, Yury Norov wrote: > This series adds API for 128-bit memory IO access and enables it for ARM64. > The original motivation for 128-bit API came from new Cavium network device > driver. The hardware requires 128-bit access to make things work. See >

[PATCH RFC 0/3] API for 128-bit IO access

Hi all, This series adds API for 128-bit memory IO access and enables it for ARM64. The original motivation for 128-bit API came from new Cavium network device driver. The hardware requires 128-bit access to make things work. See description in patch 3 for details. Also, starting from ARMv8.4,

[PATCH 3/3] arm64: enable 128-bit memory read/write support

Introduce __raw_writeo(), __raw_reado() and other arch-specific RW functions for 128-bit memory access, and enable it for arm64. 128-bit I/O is required for example by Octeon TX2 device to access some registers. According to Hardware Reference Manual: A 128-bit write to the OP_FREE0/1 registers

[PATCH 2/3] asm-generic/io.h: API for 128-bit memory accessors

Some architectures, like arm64, support 128-bit memory access. For ARM64 - using load/store pair instructions. This patch introduces reado() and writeo() functions family, where suffix 'o' stands for reading and writing the octet of bytes at once. Signed-off-by: Yury Norov

[PATCH 1/3] UAPI: Introduce 128-bit types and byteswap operations

Architectures like arm64 support 128-bit integer types and operations. This patch introduces corresponding types and __swab128() operation for be/le conversions. They are required to implement 128-bit access to the memory, in following patches. Signed-off-by: Yury Norov

[PATCH] crypto: sha512-mb - initialize pending lengths correctly

From: Eric Biggers The SHA-512 multibuffer code keeps track of the number of blocks pending in each lane. The minimum of these values is used to identify the next lane that will be completed. Unused lanes are set to a large number (0x) so that they don't affect