On Wed, 2009-09-16 at 19:58 +0200, Sebastian Andrzej Siewior wrote:
As reported by Frans Pop the new global macro W on ARM which is included
via
|arch/arm/include/asm/uaccess.h:20
|include/linux/uaccess.h:5
|include/linux/crypto.h:26
|crypto/cast6.c:23
leads to a build error because the
On Tue, May 06, 2014 at 03:48:08PM +0100, Ard Biesheuvel wrote:
On 6 May 2014 16:43, Catalin Marinas catalin.mari...@arm.com wrote:
On Thu, May 01, 2014 at 04:49:34PM +0100, Ard Biesheuvel wrote:
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index 4aef42a04bdc
On Tue, May 06, 2014 at 03:34:23PM +0100, Ard Biesheuvel wrote:
On 6 May 2014 16:31, Catalin Marinas catalin.mari...@arm.com wrote:
On Thu, May 01, 2014 at 04:49:33PM +0100, Ard Biesheuvel wrote:
Switch the default unaligned access method to 'hardware implemented
On Tue, May 06, 2014 at 04:12:55PM +0100, Catalin Marinas wrote:
On Tue, May 06, 2014 at 03:48:08PM +0100, Ard Biesheuvel wrote:
On 6 May 2014 16:43, Catalin Marinas catalin.mari...@arm.com wrote:
On Thu, May 01, 2014 at 04:49:34PM +0100, Ard Biesheuvel wrote:
diff --git a/arch/arm64
On Thu, May 01, 2014 at 04:49:35PM +0100, Ard Biesheuvel wrote:
@@ -153,12 +252,11 @@ static int fpsimd_cpu_pm_notifier(struct notifier_block
*self,
{
switch (cmd) {
case CPU_PM_ENTER:
- if (current-mm)
+ if (current-mm
On Tue, May 06, 2014 at 05:25:14PM +0100, Ard Biesheuvel wrote:
On 6 May 2014 18:08, Catalin Marinas catalin.mari...@arm.com wrote:
On Thu, May 01, 2014 at 04:49:35PM +0100, Ard Biesheuvel wrote:
@@ -153,12 +252,11 @@ static int fpsimd_cpu_pm_notifier(struct
notifier_block *self
On Thu, May 01, 2014 at 04:49:36PM +0100, Ard Biesheuvel wrote:
diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h
index 7a900142dbc8..05e1b24aca4c 100644
--- a/arch/arm64/include/asm/fpsimd.h
+++ b/arch/arm64/include/asm/fpsimd.h
@@ -41,6 +41,17 @@ struct
On Thu, May 01, 2014 at 04:49:32PM +0100, Ard Biesheuvel wrote:
This is a repost of the arm64 crypto patches that I have posted to the LAKML
over the past months. They have now been verified on actual hardware
(Cortex-A57) so if there are no remaining issues I would like to propose them
for
On 8 May 2014, at 12:22, Ard Biesheuvel ard.biesheu...@linaro.org wrote:
On 7 May 2014 16:45, Catalin Marinas catalin.mari...@arm.com wrote:
On Thu, May 01, 2014 at 04:49:32PM +0100, Ard Biesheuvel wrote:
This is a repost of the arm64 crypto patches that I have posted to the LAKML
over
On Wed, May 14, 2014 at 07:17:29PM +0100, Ard Biesheuvel wrote:
The Crypto Extensions based SHA1 implementation uses the NEON register file,
and hence runs with preemption disabled. This patch adds a TIF_NEED_RESCHED
check to its inner loop so we at least give up the CPU voluntarily when we
On 15 May 2014, at 22:35, Ard Biesheuvel ard.biesheu...@linaro.org wrote:
On 15 May 2014 10:24, Catalin Marinas catalin.mari...@arm.com wrote:
On Wed, May 14, 2014 at 07:17:29PM +0100, Ard Biesheuvel wrote:
+static u8 const *sha1_do_update(struct shash_desc *desc, const u8 *data
On Thu, May 15, 2014 at 11:10:20PM +0100, Ard Biesheuvel wrote:
On 15 May 2014 14:47, Catalin Marinas catalin.mari...@arm.com wrote:
For the time being I would drop the last 4 patches. We can revisit them
for the next kernel version.
Agreed.
Should I send an updated pull request
On Wed, Oct 22, 2014 at 08:15:32AM +0100, Ard Biesheuvel wrote:
This patch implements the AES key schedule generation using ARMv8
Crypto Instructions. It replaces the table based C implementation
in aes_generic.ko, which means we can drop the dependency on that
module.
I don't really
On Wed, May 20, 2015 at 11:27:54AM +0200, Arnd Bergmann wrote:
On Wednesday 20 May 2015 10:24:15 Catalin Marinas wrote:
On Sat, May 16, 2015 at 01:59:00AM +0200, Rafael J. Wysocki wrote:
On Friday, May 15, 2015 04:23:11 PM Suravee Suthikulpanit wrote:
+/**
+ * pci_dma_configure
On Fri, May 15, 2015 at 04:23:09PM -0500, Suravee Suthikulpanit wrote:
+static inline bool acpi_dma_is_supported(struct acpi_device *adev)
+{
+ /**
+ * Currently, we mainly support _CCA=1 (i.e. is_coherent=1)
+ * This should be equivalent to specifyig dma-coherent for
+ *
On Wed, May 20, 2015 at 02:04:02PM +0200, Arnd Bergmann wrote:
On Wednesday 20 May 2015 06:52:03 Suravee Suthikulanit wrote:
On 5/20/2015 5:01 AM, Catalin Marinas wrote:
On Fri, May 15, 2015 at 04:23:09PM -0500, Suravee Suthikulpanit wrote:
+static inline bool acpi_dma_is_supported(struct
On Thu, May 05, 2016 at 06:36:04PM +0300, Horia Geantă wrote:
> This will allow device drivers to consistently use io{read,write}XXbe
> also for 64-bit accesses.
>
> Signed-off-by: Alex Porosanu <alexandru.poros...@nxp.com>
> Signed-off-by: Horia Geantă <horia.gea...@nxp
: fix for big endian
> crypto: arm/aes-ce - fix for big endian
The changes look fine to me but I can't claim I fully understand these
algorithms. FWIW:
Acked-by: Catalin Marinas <catalin.mari...@arm.com>
(Will may pick them up for 4.9-rcX)
--
To unsubscribe from this list: send the
18 matches
Mail list logo
