from:"Hariprasad Shenai"

[PATCH net-next] chcr/cxgb4i/cxgbit/RDMA/cxgb4: Allocate resources dynamically for all cxgb4 ULD's

2016-09-16 Thread Hariprasad Shenai

Allocate resources dynamically to cxgb4's Upper layer driver's(ULD) like
cxgbit, iw_cxgb4 and cxgb4i. Allocate resources when they register with
cxgb4 driver and free them while unregistering. All the queues and the
interrupts for them will be allocated during ULD probe only and freed
during remove.

Signed-off-by: Hariprasad Shenai <haripra...@chelsio.com>
---
 drivers/crypto/chelsio/chcr_core.c |   10 +-
 drivers/infiniband/hw/cxgb4/device.c   |4 +
 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h |   47 +-
 drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c |  127 +
 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c|  613 +---
 drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.c |  223 ++--
 drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.h |   31 +-
 drivers/net/ethernet/chelsio/cxgb4/sge.c   |   18 +-
 drivers/scsi/cxgbi/cxgb4i/cxgb4i.c |3 +
 drivers/target/iscsi/cxgbit/cxgbit_main.c  |3 +
 10 files changed, 385 insertions(+), 694 deletions(-)

diff --git a/drivers/crypto/chelsio/chcr_core.c 
b/drivers/crypto/chelsio/chcr_core.c
index 2f6156b..fb5f9bb 100644
--- a/drivers/crypto/chelsio/chcr_core.c
+++ b/drivers/crypto/chelsio/chcr_core.c
@@ -39,12 +39,10 @@ static chcr_handler_func work_handlers[NUM_CPL_CMDS] = {
[CPL_FW6_PLD] = cpl_fw6_pld_handler,
 };
 
-static struct cxgb4_pci_uld_info chcr_uld_info = {
+static struct cxgb4_uld_info chcr_uld_info = {
.name = DRV_MODULE_NAME,
-   .nrxq = 4,
+   .nrxq = MAX_ULD_QSETS,
.rxq_size = 1024,
-   .nciq = 0,
-   .ciq_size = 0,
.add = chcr_uld_add,
.state_change = chcr_uld_state_change,
.rx_handler = chcr_uld_rx_handler,
@@ -205,7 +203,7 @@ static int chcr_uld_state_change(void *handle, enum 
cxgb4_state state)
 
 static int __init chcr_crypto_init(void)
 {
-   if (cxgb4_register_pci_uld(CXGB4_PCI_ULD1, _uld_info)) {
+   if (cxgb4_register_uld(CXGB4_ULD_CRYPTO, _uld_info)) {
pr_err("ULD register fail: No chcr crypto support in cxgb4");
return -1;
}
@@ -228,7 +226,7 @@ static void __exit chcr_crypto_exit(void)
kfree(u_ctx);
}
mutex_unlock(_mutex);
-   cxgb4_unregister_pci_uld(CXGB4_PCI_ULD1);
+   cxgb4_unregister_uld(CXGB4_ULD_CRYPTO);
 }
 
 module_init(chcr_crypto_init);
diff --git a/drivers/infiniband/hw/cxgb4/device.c 
b/drivers/infiniband/hw/cxgb4/device.c
index 071d733..f170b63 100644
--- a/drivers/infiniband/hw/cxgb4/device.c
+++ b/drivers/infiniband/hw/cxgb4/device.c
@@ -1475,6 +1475,10 @@ static int c4iw_uld_control(void *handle, enum 
cxgb4_control control, ...)
 
 static struct cxgb4_uld_info c4iw_uld_info = {
.name = DRV_NAME,
+   .nrxq = MAX_ULD_QSETS,
+   .rxq_size = 511,
+   .ciq = true,
+   .lro = false,
.add = c4iw_uld_add,
.rx_handler = c4iw_uld_rx_handler,
.state_change = c4iw_uld_state_change,
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h 
b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
index 4595569..1f9867d 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
@@ -437,11 +437,6 @@ enum {
MAX_ETH_QSETS = 32,   /* # of Ethernet Tx/Rx queue sets */
MAX_OFLD_QSETS = 16,  /* # of offload Tx, iscsi Rx queue sets */
MAX_CTRL_QUEUES = NCHAN,  /* # of control Tx queues */
-   MAX_RDMA_QUEUES = NCHAN,  /* # of streaming RDMA Rx queues */
-   MAX_RDMA_CIQS = 32,/* # of  RDMA concentrator IQs */
-
-   /* # of streaming iSCSIT Rx queues */
-   MAX_ISCSIT_QUEUES = MAX_OFLD_QSETS,
 };
 
 enum {
@@ -458,8 +453,7 @@ enum {
 enum {
INGQ_EXTRAS = 2,/* firmware event queue and */
/*   forwarded interrupts */
-   MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES +
-  MAX_RDMA_CIQS + MAX_ISCSIT_QUEUES + INGQ_EXTRAS,
+   MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS,
 };
 
 struct adapter;
@@ -704,10 +698,6 @@ struct sge {
struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
 
struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
-   struct sge_ofld_rxq iscsirxq[MAX_OFLD_QSETS];
-   struct sge_ofld_rxq iscsitrxq[MAX_ISCSIT_QUEUES];
-   struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
-   struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS];
struct sge_rspq fw_evtq cacheline_aligned_in_smp;
struct sge_uld_rxq_info **uld_rxq_info;
 
@@ -717,15 +707,8 @@ struct sge {
u16 max_ethqsets;   /* # of available Ethernet queue sets */
u16 ethqsets;   /* # of active Ethernet queue sets */
u16 ethtxq_rover;   /* Tx queue to clean up next */
-   u16 iscsiqsets;  /* # of active iSCSI queue sets */
-   u16 niscsitq;   /* # of available iSCST Rx queues */
-

[PATCHv3 net-next 4/4] crypto: Added Chelsio Menu to the Kconfig file

2016-08-17 Thread Hariprasad Shenai

Adds the config entry for the Chelsio Crypto Driver, Makefile changes
for the same.

Signed-off-by: Atul Gupta <atul.gu...@chelsio.com>
Signed-off-by: Hariprasad Shenai <haripra...@chelsio.com>
---
 drivers/crypto/Kconfig  |2 ++
 drivers/crypto/Makefile |1 +
 drivers/crypto/chelsio/Kconfig  |   19 +++
 drivers/crypto/chelsio/Makefile |4 
 4 files changed, 26 insertions(+), 0 deletions(-)
 create mode 100644 drivers/crypto/chelsio/Kconfig
 create mode 100644 drivers/crypto/chelsio/Makefile

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index d77ba2f..b44faf0 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -537,4 +537,6 @@ config CRYPTO_DEV_ROCKCHIP
  This driver interfaces with the hardware crypto accelerator.
  Supporting cbc/ecb chainmode, and aes/des/des3_ede cipher mode.
 
+source "drivers/crypto/chelsio/Kconfig"
+
 endif # CRYPTO_HW
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 3c6432d..ad7250f 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -31,3 +31,4 @@ obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/
 obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
 obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/
 obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/
+obj-$(CONFIG_CRYPTO_DEV_CHELSIO) += chelsio/
diff --git a/drivers/crypto/chelsio/Kconfig b/drivers/crypto/chelsio/Kconfig
new file mode 100644
index 000..2c05224
--- /dev/null
+++ b/drivers/crypto/chelsio/Kconfig
@@ -0,0 +1,19 @@
+config CRYPTO_DEV_CHELSIO
+   tristate "Chelsio Crypto Co-processor Driver"
+   depends on CHELSIO_T4 
+   select CRYPTO_SHA1
+   select CRYPTO_SHA256
+   select CRYPTO_SHA512
+   ---help---
+ The Chelsio Crypto Co-processor driver for T6 adapters.
+
+ For general information about Chelsio and our products, visit
+ our website at <http://www.chelsio.com>.
+
+ For customer support, please visit our customer support page at
+ <http://www.chelsio.com/support.html>.
+
+ Please send feedback to <linux-b...@chelsio.com>.
+
+ To compile this driver as a module, choose M here: the module
+ will be called chcr.
diff --git a/drivers/crypto/chelsio/Makefile b/drivers/crypto/chelsio/Makefile
new file mode 100644
index 000..7e4fda5
--- /dev/null
+++ b/drivers/crypto/chelsio/Makefile
@@ -0,0 +1,4 @@
+ ccflags-y := -Idrivers/net/ethernet/chelsio/cxgb4
+
+ obj-$(CONFIG_CRYPTO_DEV_CHELSIO) += chcr.o
+ chcr-objs :=  chcr_core.o chcr_algo.o
\ No newline at end of file
-- 
1.7.3

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[PATCHv3 net-next 3/4] chcr: Support for Chelsio's Crypto Hardware

2016-08-17 Thread Hariprasad Shenai

The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS

This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.

The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.

The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.

Signed-off-by: Atul Gupta <atul.gu...@chelsio.com>
Signed-off-by: Hariprasad Shenai <haripra...@chelsio.com>
---
 drivers/crypto/chelsio/chcr_algo.c   | 1525 ++
 drivers/crypto/chelsio/chcr_algo.h   |  471 +++
 drivers/crypto/chelsio/chcr_core.c   |  240 ++
 drivers/crypto/chelsio/chcr_core.h   |   80 ++
 drivers/crypto/chelsio/chcr_crypto.h |  204 +
 5 files changed, 2520 insertions(+), 0 deletions(-)
 create mode 100644 drivers/crypto/chelsio/chcr_algo.c
 create mode 100644 drivers/crypto/chelsio/chcr_algo.h
 create mode 100644 drivers/crypto/chelsio/chcr_core.c
 create mode 100644 drivers/crypto/chelsio/chcr_core.h
 create mode 100644 drivers/crypto/chelsio/chcr_crypto.h

diff --git a/drivers/crypto/chelsio/chcr_algo.c 
b/drivers/crypto/chelsio/chcr_algo.c
new file mode 100644
index 000..ad8e353
--- /dev/null
+++ b/drivers/crypto/chelsio/chcr_algo.c
@@ -0,0 +1,1525 @@
+/*
+ * This file is part of the Chelsio T6 Crypto driver for Linux.
+ *
+ * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ *
+ *  - Redistributions of source code must retain the above
+ *copyright notice, this list of conditions and the following
+ *disclaimer.
+ *
+ *  - Redistributions in binary form must reproduce the above
+ *copyright notice, this list of conditions and the following
+ *disclaimer in the documentation and/or other materials
+ *provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Written and Maintained by:
+ * Manoj Malviya (manojmalv...@chelsio.com)
+ * Atul Gupta (atul.gu...@chelsio.com)
+ * Jitendra Lulla (jlu...@chelsio.com)
+ * Yeshaswi M R Gowda (yesha...@chelsio.com)
+ * Harsh Jain (ha...@chelsio.com)
+ */
+
+#define pr_fmt(fmt) "chcr:" fmt
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "t4fw_api.h"
+#include "t4_msg.h"
+#include "chcr_core.h"
+#include "chcr_algo.h"
+#include "chcr_crypto.h"
+
+static inline struct ablk_ctx *ABLK_CTX(struct chcr_context *ctx)
+{
+   return ctx->crypto_ctx->ablkctx;
+}
+
+static inline struct hmac_ctx *HMAC_CTX(struct chcr_context *ctx)
+{
+   return ctx->crypto_ctx->hmacctx;
+}
+
+static inline struct uld_ctx *ULD_CTX(struct chcr_context *ctx)
+{
+   return ctx->dev->u_ctx;
+}
+
+static inline int is_ofld_imm(const struct sk_buff *skb)
+{
+   return (skb->len <= CRYPTO_MAX_IMM_TX_PKT_LEN);
+}
+
+/*
+ * sgl_len - calculates the size of an SGL of the given capacity
+ * @n: the number of SGL entries
+ * Calculates the number of flits needed for a scatter/gather list that
+ * can hold the given number of entries.
+ */
+static inline unsigned int sgl_len(unsigned int n)
+{
+   n--;
+   return (3 * n) / 2 + (n & 1) + 2;
+}
+
+/*
+ * chcr_handle_resp - Unmap the DMA buffers associated with the request
+ * @req: crypto request
+ */
+int chcr_handle_resp(struct crypto_async_request *req, unsigned ch

[PATCHv3 net-next 0/4] crypto/chcr: Add support for Chelsio Crypto Driver

2016-08-17 Thread Hariprasad Shenai

Hi All,

This patch series adds support for Chelsio Crypto driver. 

The patch series has been created against net-next tree and includes
patches for Chelsio Low Level Driver(cxgb4) and adds the new crypto
Upper Layer Driver(chcr) under a new directory drivers/crypto/chelsio.

Patch 1/4 ("cxgb4: Add support for dynamic allocation of resources for
ULD") adds support for dynamic allocation of resources for ULD. The
objective of this patch is to provide generic interface for upper layer
drivers to allocate and initialize hardware resources.

The present cxgb4 (network driver) apart from network functionality, also
initializes hardware and thus acts as lower layer driver for other drivers
to use hardware resources. Thus it acts as both a Low level driver for
Upper layer driver's like iw_cxgb4, cxgb4i and cxgb4it and a Network Driver.

Right now the allocation of resources for Upper layer driver's is done
statically. Patch 1/4 adds a new infrastructure for dynamic allocation of
resources. cxgb4 will read the hardware capability through firmware and
allocate/free the queues for Upper layer drivers when the respective
driver's are loaded and freed when unloaded.

Patch 2/3, 3/4 and 4/4 adds support for Chelsio Crypto Driver. The Crypto
driver will act as another ULD on top of cxgb4.

In this patch series, the ULD API framework is used only by crypto and other
ULD's will make use of it in the next series. 

This patch series is only for review, if this looks ok we will test it
thoroughly and send request for merge. 

We have included all the maintainers of respective drivers. Kindly
review the changes and provide feedback on the same.

V3: - Removed crypto queues from cxgb4 and added support for dynamic
  allocation of resources for Upper layer drivers
- Dependency fix in Kconfig.

V2: - Some residual code cleanup
- Adds pr_fmt with chcr (KBUILD_MODNAME) added
- Changes var name to accomodate them <80 columns in the chcr_register_alg
- Support for printing the crypto queue stats
- Fix compile warnings reported by kbuild bot for certain architectures
- Dependency fix in Kconfig.
- If the request has the MAY_BACKLOG bit set and hardware queue is
  full the request is queued up else -EBUSY is returned to throttle
  the user. The queue when executed and processed returns -EINPROGRESS
  in completion.

Hariprasad Shenai (4):
  cxgb4: Add support for dynamic allocation of resources for ULD
  cxgb4: Register changes and fw defines for crypto
  chcr: Support for Chelsio's Crypto Hardware
  crypto: Added Chelsio Menu to the Kconfig file

 drivers/crypto/Kconfig  |2 +
 drivers/crypto/Makefile |1 +
 drivers/crypto/chelsio/Kconfig  |   19 +
 drivers/crypto/chelsio/Makefile |4 +
 drivers/crypto/chelsio/chcr_algo.c  | 1525 +++
 drivers/crypto/chelsio/chcr_algo.h  |  471 +++
 drivers/crypto/chelsio/chcr_core.c  |  240 
 drivers/crypto/chelsio/chcr_core.h  |   80 ++
 drivers/crypto/chelsio/chcr_crypto.h|  204 +++
 drivers/net/ethernet/chelsio/cxgb4/Makefile |2 +-
 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h  |   59 +-
 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c |  153 ++-
 drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.c  |  555 
 drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.h  |   34 +-
 drivers/net/ethernet/chelsio/cxgb4/sge.c|4 +-
 drivers/net/ethernet/chelsio/cxgb4/t4_msg.h |  437 +++
 drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h   |  126 ++-
 17 files changed, 3866 insertions(+), 50 deletions(-)
 create mode 100644 drivers/crypto/chelsio/Kconfig
 create mode 100644 drivers/crypto/chelsio/Makefile
 create mode 100644 drivers/crypto/chelsio/chcr_algo.c
 create mode 100644 drivers/crypto/chelsio/chcr_algo.h
 create mode 100644 drivers/crypto/chelsio/chcr_core.c
 create mode 100644 drivers/crypto/chelsio/chcr_core.h
 create mode 100644 drivers/crypto/chelsio/chcr_crypto.h
 create mode 100644 drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.c

-- 
1.7.3

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[PATCHv3 net-next 2/4] cxgb4: Register changes and fw defines for crypto

2016-08-17 Thread Hariprasad Shenai

Signed-off-by: Atul Gupta <atul.gu...@chelsio.com>
Signed-off-by: Hariprasad Shenai <haripra...@chelsio.com>
---
 drivers/net/ethernet/chelsio/cxgb4/t4_msg.h   |  437 +
 drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h |  124 +++
 2 files changed, 561 insertions(+), 0 deletions(-)

diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_msg.h 
b/drivers/net/ethernet/chelsio/cxgb4/t4_msg.h
index 4705e2d..7a2be51 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_msg.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_msg.h
@@ -61,6 +61,7 @@ enum {
CPL_ABORT_REQ_RSS = 0x2B,
CPL_ABORT_RPL_RSS = 0x2D,
 
+   CPL_RX_PHYS_ADDR  = 0x30,
CPL_CLOSE_CON_RPL = 0x32,
CPL_ISCSI_HDR = 0x33,
CPL_RDMA_CQE  = 0x35,
@@ -83,6 +84,10 @@ enum {
CPL_PASS_OPEN_REQ6= 0x81,
CPL_ACT_OPEN_REQ6 = 0x83,
 
+   CPL_TX_TLS_PDU =0x88,
+   CPL_TX_SEC_PDU= 0x8A,
+   CPL_TX_TLS_ACK= 0x8B,
+
CPL_RDMA_TERMINATE= 0xA2,
CPL_RDMA_WRITE= 0xA4,
CPL_SGE_EGR_UPDATE= 0xA5,
@@ -94,6 +99,8 @@ enum {
CPL_FW4_PLD   = 0xC1,
CPL_FW4_ACK   = 0xC3,
 
+   CPL_RX_PHYS_DSGL  = 0xD0,
+
CPL_FW6_MSG   = 0xE0,
CPL_FW6_PLD   = 0xE1,
CPL_TX_PKT_LSO= 0xED,
@@ -1360,6 +1367,15 @@ struct ulptx_idata {
__be32 len;
 };
 
+struct ulp_txpkt {
+   __be32 cmd_dest;
+   __be32 len;
+};
+
+#define ULPTX_CMD_S24
+#define ULPTX_CMD_M0xFF
+#define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
+
 #define ULPTX_NSGE_S0
 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
 
@@ -1367,6 +1383,22 @@ struct ulptx_idata {
 #define ULPTX_MORE_V(x)((x) << ULPTX_MORE_S)
 #define ULPTX_MORE_F   ULPTX_MORE_V(1U)
 
+#define ULP_TXPKT_DEST_S16
+#define ULP_TXPKT_DEST_M0x3
+#define ULP_TXPKT_DEST_V(x) ((x) << ULP_TXPKT_DEST_S)
+
+#define ULP_TXPKT_FID_S 4
+#define ULP_TXPKT_FID_M 0x7ff
+#define ULP_TXPKT_FID_V(x)  ((x) << ULP_TXPKT_FID_S)
+
+#define ULP_TXPKT_RO_S  3
+#define ULP_TXPKT_RO_V(x) ((x) << ULP_TXPKT_RO_S)
+#define ULP_TXPKT_RO_F ULP_TXPKT_RO_V(1U)
+
+#define ULP_TX_SC_MORE_S 23
+#define ULP_TX_SC_MORE_V(x) ((x) << ULP_TX_SC_MORE_S)
+#define ULP_TX_SC_MORE_F  ULP_TX_SC_MORE_V(1U)
+
 struct ulp_mem_io {
WR_HDR;
__be32 cmd;
@@ -1404,4 +1436,409 @@ struct ulp_mem_io {
 #define ULP_MEMIO_DATA_LEN_S0
 #define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S)
 
+#define ULPTX_NSGE_S0
+#define ULPTX_NSGE_M0x
+#define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
+#define ULPTX_NSGE_G(x) (((x) >> ULPTX_NSGE_S) & ULPTX_NSGE_M)
+
+struct ulptx_sc_memrd {
+   __be32 cmd_to_len;
+   __be32 addr;
+};
+
+#define ULP_TXPKT_DATAMODIFY_S   23
+#define ULP_TXPKT_DATAMODIFY_M   0x1
+#define ULP_TXPKT_DATAMODIFY_V(x)((x) << ULP_TXPKT_DATAMODIFY_S)
+#define ULP_TXPKT_DATAMODIFY_G(x)\
+   (((x) >> ULP_TXPKT_DATAMODIFY_S) & ULP_TXPKT_DATAMODIFY__M)
+#define ULP_TXPKT_DATAMODIFY_F   ULP_TXPKT_DATAMODIFY_V(1U)
+
+#define ULP_TXPKT_CHANNELID_S22
+#define ULP_TXPKT_CHANNELID_M0x1
+#define ULP_TXPKT_CHANNELID_V(x) ((x) << ULP_TXPKT_CHANNELID_S)
+#define ULP_TXPKT_CHANNELID_G(x) \
+   (((x) >> ULP_TXPKT_CHANNELID_S) & ULP_TXPKT_CHANNELID_M)
+#define ULP_TXPKT_CHANNELID_FULP_TXPKT_CHANNELID_V(1U)
+
+#define SCMD_SEQ_NO_CTRL_S  29
+#define SCMD_SEQ_NO_CTRL_M  0x3
+#define SCMD_SEQ_NO_CTRL_V(x)   ((x) << SCMD_SEQ_NO_CTRL_S)
+#define SCMD_SEQ_NO_CTRL_G(x)   \
+   (((x) >> SCMD_SEQ_NO_CTRL_S) & SCMD_SEQ_NO_CTRL_M)
+
+/* StsFieldPrsnt- Status field at the end of the TLS PDU */
+#define SCMD_STATUS_PRESENT_S   28
+#define SCMD_STATUS_PRESENT_M   0x1
+#define SCMD_STATUS_PRESENT_V(x)((x) << SCMD_STATUS_PRESENT_S)
+#define SCMD_STATUS_PRESENT_G(x)\
+   (((x) >> SCMD_STATUS_PRESENT_S) & SCMD_STATUS_PRESENT_M)
+#define SCMD_STATUS_PRESENT_F   SCMD_STATUS_PRESENT_V(1U)
+
+/* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic,
+ * 3-15: Reserved.
+ */
+#define SCMD_PROTO_VERSION_S24
+#define SCMD_PROTO_VERSION_M0xf
+#define SCMD_PROTO_VERSION_V(x) ((x) << SCMD_PROTO_VERSION_S)
+#define SCMD_PROTO_VERSION_G(x) \
+   (((x) >> SCMD_PROTO_VERSION_S) & SCMD_PROTO_VERSION_M)
+
+/* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */
+#define SCMD_ENC_DEC_CTRL_S 23
+#define SCMD_ENC_DEC_CTRL_M 0x1
+#define SCMD_ENC_DEC_CTRL_V(x)  ((x) << SCMD_ENC_DEC_CTRL_S)
+#define SCMD_ENC_DEC_CTRL_G(x)  \
+   (((x) >> SCMD_ENC_DEC_CTRL_S) & SCMD_ENC_DEC_CTRL_M)
+#define SCMD_ENC_DEC_CTRL_F SCMD_ENC_DEC_CTRL_V(1U)
+
+/* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */
+#define SC

[PATCHv3 net-next 1/4] cxgb4: Add support for dynamic allocation of resources for ULD

2016-08-17 Thread Hariprasad Shenai

Add a new commmon infrastructure to allocate reosurces dynamically to
Upper layer driver's(ULD) when they register with cxgb4 driver and free
them during unregistering. All the queues and the interrupts for
them will be allocated during ULD probe only and freed during remove.

Signed-off-by: Atul Gupta <atul.gu...@chelsio.com>
Signed-off-by: Hariprasad Shenai <haripra...@chelsio.com>
---
 drivers/net/ethernet/chelsio/cxgb4/Makefile |2 +-
 drivers/net/ethernet/chelsio/cxgb4/cxgb4.h  |   59 +++-
 drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c |  153 +--
 drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.c  |  555 +++
 drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.h  |   34 ++-
 drivers/net/ethernet/chelsio/cxgb4/sge.c|4 +-
 drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h   |2 +-
 7 files changed, 759 insertions(+), 50 deletions(-)
 create mode 100644 drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.c

diff --git a/drivers/net/ethernet/chelsio/cxgb4/Makefile 
b/drivers/net/ethernet/chelsio/cxgb4/Makefile
index 85c9282..e955eda 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/Makefile
+++ b/drivers/net/ethernet/chelsio/cxgb4/Makefile
@@ -4,7 +4,7 @@
 
 obj-$(CONFIG_CHELSIO_T4) += cxgb4.o
 
-cxgb4-objs := cxgb4_main.o l2t.o t4_hw.o sge.o clip_tbl.o cxgb4_ethtool.o
+cxgb4-objs := cxgb4_main.o l2t.o t4_hw.o sge.o clip_tbl.o cxgb4_ethtool.o 
cxgb4_uld.o
 cxgb4-$(CONFIG_CHELSIO_T4_DCB) +=  cxgb4_dcb.o
 cxgb4-$(CONFIG_CHELSIO_T4_FCOE) +=  cxgb4_fcoe.o
 cxgb4-$(CONFIG_CHELSIO_T4_UWIRE) +=  cxgb4_ppm.o
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h 
b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
index 7ce076f..94d7592 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
@@ -53,6 +53,8 @@
 #include "cxgb4_uld.h"
 
 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
+extern struct list_head adapter_list;
+extern struct mutex uld_mutex;
 
 enum {
MAX_NPORTS  = 4, /* max # of ports */
@@ -338,6 +340,7 @@ struct adapter_params {
enum chip_type chip;   /* chip code */
struct arch_specific_params arch;  /* chip specific params */
unsigned char offload;
+   unsigned char crypto;   /* HW capability for crypto */
 
unsigned char bypass;
 
@@ -403,7 +406,6 @@ struct fw_info {
struct fw_hdr fw_hdr;
 };
 
-
 struct trace_params {
u32 data[TRACE_LEN / 4];
u32 mask[TRACE_LEN / 4];
@@ -509,6 +511,10 @@ enum { /* adapter flags */
FW_OFLD_CONN   = (1 << 9),
 };
 
+enum {
+   ULP_CRYPTO_LOOKASIDE = 1 << 0,
+};
+
 struct rx_sw_desc;
 
 struct sge_fl { /* SGE free-buffer queue state */
@@ -679,6 +685,16 @@ struct sge_ctrl_txq {   /* state for an SGE 
control Tx queue */
u8 full;/* the Tx ring is full */
 } cacheline_aligned_in_smp;
 
+struct sge_uld_rxq_info {
+   char name[IFNAMSIZ];/* name of ULD driver */
+   struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */
+   u16 *msix_tbl;  /* msix_tbl for uld */
+   u16 *rspq_id;   /* response queue id's of rxq */
+   u16 nrxq;   /* # of ingress uld queues */
+   u16 nciq;   /* # of completion queues */
+   u8 uld; /* uld type */
+};
+
 struct sge {
struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
@@ -690,6 +706,7 @@ struct sge {
struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS];
struct sge_rspq fw_evtq cacheline_aligned_in_smp;
+   struct sge_uld_rxq_info **uld_rxq_info;
 
struct sge_rspq intrq cacheline_aligned_in_smp;
spinlock_t intrq_lock;
@@ -701,6 +718,7 @@ struct sge {
u16 niscsitq;   /* # of available iSCST Rx queues */
u16 rdmaqs; /* # of available RDMA Rx queues */
u16 rdmaciqs;   /* # of available RDMA concentrator IQs */
+   u16 nqs_per_uld;/* # of Rx queues per ULD */
u16 iscsi_rxq[MAX_OFLD_QSETS];
u16 iscsit_rxq[MAX_ISCSIT_QUEUES];
u16 rdma_rxq[MAX_RDMA_QUEUES];
@@ -756,6 +774,17 @@ struct hash_mac_addr {
u8 addr[ETH_ALEN];
 };
 
+struct uld_msix_bmap {
+   unsigned long *msix_bmap;
+   unsigned int mapsize;
+   spinlock_t lock; /* lock for acquiring bitmap */
+};
+
+struct uld_msix_info {
+   unsigned short vec;
+   char desc[IFNAMSIZ + 10];
+};
+
 struct adapter {
void __iomem *regs;
void __iomem *bar2;
@@ -778,6 +807,9 @@ struct adapter {
unsigned short vec;
char desc[IFNAMSIZ + 10];
} msix_info[MAX_INGQ + 1];
+   struct uld_msix_info *msix_info_ulds; /* msix info for uld's */
+   struct uld_msi

Re: [Patch-V2 2/3] chcr: Support for Chelsio's Crypto Hardware

2016-08-17 Thread Hariprasad Shenai

On Tue, Jul 19, 2016 at 09:15:22PM -0700, David Miller wrote:
> From: Yeshaswi M R Gowda 
> Date: Mon, 18 Jul 2016 22:42:14 -0700
> 
> > +config CRYPTO_DEV_CHELSIO
> > +   tristate "Chelsio Crypto Co-processor Driver"
> > +   depends on PCI && NETDEVICES && ETHERNET
> > +   select CRYPTO_SHA1
> > +   select CRYPTO_SHA256
> > +   select CRYPTO_SHA512
> > +   select NET_VENDOR_CHELSIO
> > +   select CHELSIO_T4
> 
> The user shouldn't have to know about the technical details about
> how this chip is physically implemented.
> 
> It's therefore not reasonable to require an ethernet driver to be
> enabled to use the crypto engine.
> 
> Also, selecting Kconfig symbol X does not recursively enable the
> "select" statement(s) of symbol X nor does it check symbol X's
> dependencies.
> 
> This is really one big huge dependency mess, and I think you have
> to split out the core of the T4 driver into a driver subtype
> agnostic library or similar to make this work properly.
> 
> Don't just shoehorn this stuff into the ethernet driver.  Round
> peg, square hole.
> 

Hi David,

We looked at the interface exposed by the current Ethernet driver and
how other drivers/protocols use that for exchanging control/data with
hardware. The cxgb4 driver is more than a Ethernet driver, it also
initializes the hardware so that other protocols can use them.
We have a terminology called lower level driver(LLD) and
Upper level driver(ULD). The lower level driver, which is cxgb4 acts
both as Ethernet driver and enables the hardware resources for ULD.
The ULD's such as iSCSI/iWARP/Crypto depends on lower level driver for the
initializied harware resources before processing the protocol specific part.

In v3 series of patch we have introduced common API framework for upper
level drivers to use the hardware resources. At present, all resouces are
allocated statically, no matter whether ULD is loaded or not. With the new
framework, all allocations and initialization for respective ULD's are done,
when they register with the LLD and freed when unregistered.

The ULD API framework makes the interface flexible and scalable for any new
driver which shall run on top of cxgb4. The v3 patch uses the new ULD APIs
introduced by cxgb4 only for crypto, and shall be extended further for
iSCSI and iWARP in upcoming series. The API also saves new driver(ULD) from
exclusively requesting the PCI function and manage the resources associated.

Thanks,
Hari
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[PATCH net-next] chcr/cxgb4i/cxgbit/RDMA/cxgb4: Allocate resources dynamically for all cxgb4 ULD's

[PATCHv3 net-next 4/4] crypto: Added Chelsio Menu to the Kconfig file

[PATCHv3 net-next 3/4] chcr: Support for Chelsio's Crypto Hardware

[PATCHv3 net-next 0/4] crypto/chcr: Add support for Chelsio Crypto Driver

[PATCHv3 net-next 2/4] cxgb4: Register changes and fw defines for crypto

[PATCHv3 net-next 1/4] cxgb4: Add support for dynamic allocation of resources for ULD

Re: [Patch-V2 2/3] chcr: Support for Chelsio's Crypto Hardware

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