On 3/16/2021 7:02 PM, Ahmad Fatoum wrote:
[...]
> +struct trusted_key_ops caam_trusted_key_ops = {
> + .migratable = 0, /* non-migratable */
> + .init = trusted_caam_init,
> + .seal = trusted_caam_seal,
> + .unseal = trusted_caam_unseal,
> + .exit = trusted_caam_exit,
> +};
caam
On 3/16/2021 7:01 PM, Ahmad Fatoum wrote:
> +int caam_encap_blob(struct caam_blob_priv *priv, const char *keymod,
> + void *input, void *output, size_t length)
> +{
> + u32 *desc;
> + struct device *jrdev = &priv->jrdev;
> + dma_addr_t dma_in, dma_out;
> + struct caa
On 3/16/2021 7:02 PM, Ahmad Fatoum wrote:
> The Cryptographic Acceleration and Assurance Module (CAAM) is an IP core
> built into many newer i.MX and QorIQ SoCs by NXP.
>
> Its blob mechanism can AES encrypt/decrypt user data using a unique
> never-disclosed device-specific key. There has been mul
aamalg_qi2.c:87: warning: Function parameter or member
> 'xts_key_fallback' not described in 'caam_ctx'
> drivers/crypto/caam/caamalg_qi2.c:87: warning: Function parameter or member
> 'fallback' not described in 'caam_ctx'
>
> Cc: "Horia Ge
inux.org.uk
https://lore.kernel.org/lkml/20191010083503.250941...@linuxfoundation.org
https://lore.kernel.org/linux-mmc/am7pr04mb688507b5b4d84eb266738891f8...@am7pr04mb6885.eurprd04.prod.outlook.com
Thanks,
Horia
-- >8 --
Subject: [PATCH] arm64: dts: ls1046a: mark crypto engine dma coheren
aamalg_qi2.c:87: warning: Function parameter or member
> 'xts_key_fallback' not described in 'caam_ctx'
> drivers/crypto/caam/caamalg_qi2.c:87: warning: Function parameter or member
> 'fallback' not described in 'caam_ctx'
>
> Cc: "Horia Ge
On 3/3/2021 2:07 PM, Robin Murphy wrote:
> On 2021-03-03 10:26, Horia Geantă wrote:
>> Adding some people in the loop, maybe they could help in understanding
>> why lack of "dma-coherent" property for a HW-coherent device could lead to
>> unexpected / strange side
On 3/3/2021 4:57 PM, Sascha Hauer wrote:
> On Wed, Mar 03, 2021 at 12:26:32PM +0200, Horia Geantă wrote:
>> Adding some people in the loop, maybe they could help in understanding
>> why lack of "dma-coherent" property for a HW-coherent device could lead to
>> un
ev/hwrng etc.?
3. Try dumping some of the RNG registers using below patch:
-- >8 --
Subject: [PATCH] crypto: caam - rng debugging
Dump RNG registers at hwrng.init time and in case descriptor returns
RNG HW error.
Signed-off-by: Horia Geantă
---
drivers/crypto/caam/caamrng.c | 9 -
:87: warning: Function parameter or member
> 'fallback' not described in 'caam_ctx'
>
> Cc: "Horia Geantă"
> Cc: Aymen Sghaier
> Cc: Herbert Xu
> Cc: "David S. Miller"
> Cc: linux-crypto@vger.kernel.org
> Signed-off-by: Lee Jones
>
On 2/4/2021 1:10 PM, Lee Jones wrote:
> Fixes the following W=1 kernel build warning(s):
>
> drivers/crypto/caam/caampkc.c:199: warning: expecting prototype for from a
> given scatterlist(). Prototype was for caam_rsa_count_leading_zeros() instead
>
> Cc: "Horia Geant
gt; should be defined with DEFINE_DEBUGFS_ATTRIBUTE.
>
> Reported-by: Abaci Robot
> Signed-off-by: Jiapeng Chong
Reviewed-by: Horia Geantă
Thanks,
Horia
gt; should be defined with DEFINE_DEBUGFS_ATTRIBUTE.
>
> Reported-by: Abaci Robot
> Signed-off-by: Jiapeng Chong
Reviewed-by: Horia Geantă
Patch title nitpick:
s/crypto: caam -Replace/crypto: caam - Replace
Thanks,
Horia
>
> Signed-off-by: Romain Perier
> Signed-off-by: Allen Pais
Reviewed-by: Horia Geantă
Thanks,
Horia
On 12/3/2020 3:35 AM, Iuliana Prodan (OSS) wrote:
> From: Iuliana Prodan
>
> This series removes CRYPTO_ALG_ALLOCATES_MEMORY flag and
> allocates the memory needed by the driver, to fulfil a
> request, within the crypto request object.
> The extra size needed for base extended descriptor, hw
> de
On 11/26/2020 9:09 AM, Ard Biesheuvel wrote:
> On Wed, 25 Nov 2020 at 22:39, Iuliana Prodan wrote:
>>
>> On 11/25/2020 11:16 PM, Ard Biesheuvel wrote:
>>> On Wed, 25 Nov 2020 at 22:14, Iuliana Prodan (OSS)
>>> wrote:
From: Iuliana Prodan
Add the option to allocate the crypto
On 11/17/2019 2:57 AM, Herbert Xu wrote:
> On Sun, Nov 17, 2019 at 12:01:20AM +0100, Maciej S. Szmigiero wrote:
>>
>> If a reader (user space) task is frozen then it is no longer waiting
>> on this waitqueue - at least if I understand correctly how the freezer
>> works for user space tasks, that is
- >8 --
Subject: [PATCH] crypto: caam/qi - simplify error path for context allocation
Wang Qing reports that IS_ERR_OR_NULL() should be matched with
PTR_ERR_OR_ZERO(), not PTR_ERR().
As it turns out, the error path always returns an error code,
i.e. NULL is never returned.
Update the code accord
hould be scheduled.
>
> Signed-off-by: Sebastian Andrzej Siewior
> Cc: "Horia Geantă"
> Cc: Aymen Sghaier
> Cc: Herbert Xu
> Cc: "David S. Miller"
> Cc: Madalin Bucur
> Cc: Jakub Kicinski
> Cc: Li Yang
> Cc: linux-crypto@vger.kernel.org
happens now) but could be changed if it is wrong
> due to `budget' handling.
>
Looks good to me.
> Add an argument to __poll_portal_fast() which is true if NAPI needs to be
> scheduled. This requires propagating the value to the caller including
> `qman_cb_dqrr' typedef whi
quot;crypto: caam/jr - add fallback for XTS with more than 8B
IV")
Fixes: 83e8aa912138 ("crypto: caam/qi - add fallback for XTS with more than 8B
IV")
Fixes: 36e2d7cfdcf1 ("crypto: caam/qi2 - add fallback for XTS with more than 8B
IV")
Signed-off-by: Horia Geant
algorithm.
Fixes: 00b99ad2bac2 ("crypto: arm/aes-neonbs - Use generic cbc encryption path")
Signed-off-by: Horia Geantă
---
arch/arm/crypto/aes-neonbs-glue.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/crypto/aes-neonbs-glue.c
b/arch/arm/crypto/
On 10/28/2020 11:07 AM, Ard Biesheuvel wrote:
> On Wed, 28 Oct 2020 at 10:03, Horia Geantă wrote:
>>
>> Loading the module deadlocks since:
>> -local cbc(aes) implementation needs a fallback and
>> -crypto API tries to find one but the request_module() resolves
d for the
> non-crypto-API requests that are not passed through crypto-engine).
>
> The callback for do_batch_requests is NULL, since CAAM
> doesn't support linked requests.
>
> Signed-off-by: Iuliana Prodan
Reviewed-by: Horia Geantă
Thanks,
Horia
On 10/26/2020 7:11 PM, Iuliana Prodan wrote:
> On 10/26/2020 5:36 PM, Horia Geantă wrote:
>> On 10/21/2020 11:07 PM, Iuliana Prodan wrote:
[...]
>>> +#define CRYPTO_ENGINE_MAX_QLEN (2 * (JOBR_DEPTH - THRESHOLD))
>>> +
>> What's the logic behind multiplying by
On 10/21/2020 11:07 PM, Iuliana Prodan wrote:
> Use the new crypto_engine_alloc_init_and_set() function to
> initialize crypto-engine and enable retry mechanism.
>
> Set the maximum size for crypto-engine software queue based on
> Job Ring size (JOBR_DEPTH) and a threshold (reserved for the
> non-
c.c | 27 ---
> drivers/crypto/caam/caamalg_qi.c | 94 +---
> drivers/crypto/caam/caamalg_qi2.c | 111 ++---
> drivers/crypto/caam/caamalg_qi2.h | 2 +
> 6 files changed, 293 insertions(+), 38 deletions(-)
>
For the series:
Reviewed-by: Horia Geantă
Thanks,
Horia
On 9/21/2020 10:32 AM, Andrei Botila (OSS) wrote:
> From: Andrei Botila
>
> This patch series fixes some problems in CAAM's implementation of xts(aes):
> - CAAM until Era 9 can't process XTS with 16B IV
> - CAAM can only process in hardware XTS key lengths of 16B and 32B
> - These hardware lim
On 9/21/2020 10:32 AM, Andrei Botila (OSS) wrote:
> +static bool xts_skcipher_ivsize(struct skcipher_request *req)
> +{
> + struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
> + unsigned int ivsize = crypto_skcipher_ivsize(skcipher);
> + u64 size = 0;
> +
> + size = ge
On 9/16/2020 12:50 AM, Richard Weinberger wrote:
> - Ursprüngliche Mail -
>> Von: "horia geanta"
How to use it with cryptsetup?
I'm asking because it is not clear to me why you are not implementing
a new kernel key type (KEYS subsystem)
to utilize tagged keys.
Many
On 9/18/2020 4:30 AM, Qinglang Miao wrote:
> Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code.
>
> Signed-off-by: Qinglang Miao
Reviewed-by: Horia Geantă
Thanks,
Horia
On 9/14/2020 9:38 AM, Richard Weinberger wrote:
> On Thu, Jul 16, 2020 at 4:12 PM Richard Weinberger
> wrote:
>>
>> On Mon, Jul 13, 2020 at 12:09 AM Iuliana Prodan
>> wrote:
>>>
>>> Tagged keys are keys that contain metadata indicating what
>>> they are and how to handle them using tag_object AP
On 9/15/2020 1:26 PM, Ard Biesheuvel wrote:
> On Tue, 15 Sep 2020 at 13:02, Horia Geantă wrote:
>>
>> On 9/14/2020 9:20 PM, Ard Biesheuvel wrote:
>>> On Mon, 14 Sep 2020 at 20:12, Horia Geantă wrote:
>>>>
>>>> On 9/14/2020 7:28 PM, Ard Biesheuvel
On 9/14/2020 9:20 PM, Ard Biesheuvel wrote:
> On Mon, 14 Sep 2020 at 20:12, Horia Geantă wrote:
>>
>> On 9/14/2020 7:28 PM, Ard Biesheuvel wrote:
>>> On Mon, 14 Sep 2020 at 19:24, Horia Geantă wrote:
>>>>
>>>> On 9/9/2020 1:10 AM, Herbert Xu wrote
On 9/14/2020 7:28 PM, Ard Biesheuvel wrote:
> On Mon, 14 Sep 2020 at 19:24, Horia Geantă wrote:
>>
>> On 9/9/2020 1:10 AM, Herbert Xu wrote:
>>> On Tue, Sep 08, 2020 at 01:35:04PM +0300, Horia Geantă wrote:
>>>>
>>>>> Just go with the get_unal
On 9/9/2020 1:10 AM, Herbert Xu wrote:
> On Tue, Sep 08, 2020 at 01:35:04PM +0300, Horia Geantă wrote:
>>
>>> Just go with the get_unaligned unconditionally.
>>
>> Won't this lead to sub-optimal code for ARMv7
>> in case the IV is aligned?
>
> If thi
On 8/21/2020 6:47 AM, Herbert Xu wrote:
> On Thu, Aug 06, 2020 at 07:35:43PM +0300, Andrei Botila wrote:
>>
>> +static bool xts_skcipher_ivsize(struct skcipher_request *req)
>> +{
>> +struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
>> +unsigned int ivsize = crypto_skcipher_i
On 8/21/2020 6:47 AM, Herbert Xu wrote:
> On Tue, Aug 11, 2020 at 05:30:41PM +0300, Horia Geantă wrote:
>>
>>> + if (IS_ERR(fallback)) {
>>> + pr_err("Failed to allocate %s fallback: %ld\n",
>>> +
On 8/10/2020 8:03 PM, Eric Biggers wrote:
> On Mon, Aug 10, 2020 at 05:33:39PM +0300, Horia Geantă wrote:
>> On 8/10/2020 4:45 PM, Herbert Xu wrote:
>>> On Mon, Aug 10, 2020 at 10:20:20AM +, Van Leeuwen, Pascal wrote:
>>>>
>>>> With all due respect
On 8/6/2020 7:36 PM, Andrei Botila (OSS) wrote:
> @@ -1790,7 +1792,9 @@ static inline int skcipher_crypt(struct
> skcipher_request *req, bool encrypt)
> if (!req->cryptlen)
> return 0;
>
> - if (ctx->fallback && xts_skcipher_ivsize(req)) {
> + if (ctx->fallback && (xt
On 8/6/2020 7:36 PM, Andrei Botila (OSS) wrote:
> @@ -3344,12 +3382,30 @@ static int caam_cra_init(struct crypto_skcipher *tfm)
> struct caam_skcipher_alg *caam_alg =
> container_of(alg, typeof(*caam_alg), skcipher);
> struct caam_ctx *ctx = crypto_skcipher_ctx(tfm);
> +
On 8/11/2020 3:59 AM, Herbert Xu wrote:
> On Mon, Aug 10, 2020 at 07:47:40PM +0300, Horia Geantă wrote:
>>
>> I would prefer keeping the caam rfc3686(ctr(aes)) implementation.
>> It's almost cost-free when compared to ctr(aes), since:
>> -there are no (acce
On 7/28/2020 10:19 AM, Herbert Xu wrote:
> The rfc3686 implementations in caam are pretty much the same
> as the generic rfc3686 wrapper. So they can simply be removed
> to reduce complexity.
>
I would prefer keeping the caam rfc3686(ctr(aes)) implementation.
It's almost cost-free when compared t
ed-off-by: Herbert Xu
Reviewed-by: Horia Geantă
Thanks,
Horia
On 7/28/2020 10:19 AM, Herbert Xu wrote:
> @@ -40,30 +39,41 @@ static int chacha_stream_xor(struct skcipher_request *req,
> static int crypto_chacha_crypt(struct skcipher_request *req)
> {
> struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
> + struct chacha_reqctx *rctx = skci
On 8/10/2020 4:45 PM, Herbert Xu wrote:
> On Mon, Aug 10, 2020 at 10:20:20AM +, Van Leeuwen, Pascal wrote:
>>
>> With all due respect, but this makes no sense.
>
> I agree. This is a lot of churn for no gain.
>
I would say the gain is that all skcipher algorithms would behave the same
when i
On 8/1/2020 3:42 PM, Herbert Xu wrote:
> On Fri, Jul 31, 2020 at 07:46:07PM +0300, Horia Geantă wrote:
>>
>> Below hunk is needed for fixing the compilation when CONFIG_DEBUG_FS=y:
>
> Thanks for catching this. The NULL pointer assignments are also
> a bit iffy. So he
On 7/30/2020 4:54 PM, Herbert Xu wrote:
> Currently the debugfs fops are defined in caam/intern.h. This causes
> problems because it creates identical static functions and variables
> in multiple files. It also creates warnings when those files don't
> use the fops.
>
Indeed, I see the warnings
caam crypto module is included in several ARMv7-based SoCs from
i.MX, Layerscape, Vybrid families.
Signed-off-by: Horia Geantă
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
enabled).
Also see commit ec2a844ef7c1
("ARM: dts: imx7s: add snvs rtc clock")
for a similar fix.
Signed-off-by: André Draszik
Acked-by: Rob Herring
Reviewed-by: Horia Geantă
Signed-off-by: Horia Geantă
---
.../devicetree/bindings/crypto/fsl-sec4.txt | 17 +
ystem will
assume the interrupt was handled successfully even though it wasn't
at all.
Signed-off-by: André Draszik
Reviewed-by: Horia Geantă
Signed-off-by: Horia Geantă
---
drivers/input/keyboard/snvs_pwrkey.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git
Hi Herbert, Dmitry,
This is a resend of v2 patches 1,5,6 that were not picked up
https://lore.kernel.org/linux-input/20200225161201.1975-1-...@andred.net
with collecting Acked-by, Reviewed-by.
I skipped Robin's Reviewed-by since I prefer avoiding misintepreting
the discussion between him and Andr
er.
Signed-off-by: André Draszik
Reviewed-by: Horia Geantă
Signed-off-by: Horia Geantă
---
drivers/input/keyboard/snvs_pwrkey.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/input/keyboard/snvs_pwrkey.c
b/drivers/input/keyboard/snvs_pw
On 7/22/2020 3:15 PM, Horia Geantă wrote:
> In some cases, e.g. when TRNG is not properly configured,
> the RNG module could issue a "Hardware error" at runtime.
>
> "Continuos check" error is emitted when some of the BISTs fail.
>
> Signed-off-by: Horia
From: Franck LENORMAND
When building on a platform with a 32bit DMA address, taking the
upper 32 bits makes no sense.
Signed-off-by: Franck LENORMAND
Signed-off-by: Horia Geantă
---
drivers/crypto/caam/regs.h | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a
Add a module alias, to enable udev-based module autoloading:
$ modinfo -F alias drivers/crypto/caam/dpaa2_caam.ko
fsl-mc:v1957ddpseci
Signed-off-by: Horia Geantă
---
drivers/crypto/caam/caamalg_qi2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/crypto/caam/caamalg_qi2.c
b
In some cases, e.g. when TRNG is not properly configured,
the RNG module could issue a "Hardware error" at runtime.
"Continuos check" error is emitted when some of the BISTs fail.
Signed-off-by: Horia Geantă
Signed-off-by: Horia Geantă
---
drivers/crypto/caam/error.c | 3
From: Dan Douglass
caam_jr_register() function is no longer part of the driver since
commit 6dad41158db6 ("crypto: caam - Remove unused functions from Job Ring")
This patch removes a comment referencing the function.
Signed-off-by: Dan Douglass
Signed-off-by: Horia Geantă
---
driv
In case of bad key length, driver emits "key size mismatch" messages,
but only for xts(aes) algorithms.
Reduce verbosity by making them visible only when debugging.
This way crypto fuzz testing log cleans up a bit.
Signed-off-by: Horia Geantă
---
drivers/crypto/caam/caamalg
am/jr top-level library)
commit 9a2537d0ebc9 ("crypto: caam - create ahash shared descriptors only once")
Signed-off-by: Horia Geantă
---
drivers/crypto/caam/caamalg_qi2.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/caam/caamalg_qi2.c
b/driv
Fix error reporting when preparation of an hmac algorithm
for registration fails: print the hmac algorithm name, not the unkeyed
hash algorithm name.
Signed-off-by: Horia Geantă
---
drivers/crypto/caam/caamalg_qi2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
Horia Geantă (5):
crypto: caam/qi2 - fix error reporting for caam_hash_alloc
crypto: caam/qi2 - create ahash shared descriptors only once
crypto: caam - silence .setkey in case of bad key length
crypto: caam - add more RNG hw error codes
crypto: caam/qi2 - add module alias
drivers/crypto
On 7/16/2020 12:00 PM, Qinglang Miao wrote:
> From: Liu Shixin
>
> Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code.
>
> Signed-off-by: Liu Shixin
Reviewed-by: Horia Geantă
This patch depends on linux-next
commit 4d4901c6d748 ("seq_file: switch over direct seq_
On 7/16/2020 2:55 PM, Herbert Xu wrote:
> Eric Biggers wrote:
>> This series introduces a flag that algorithms can set to indicate that
>> they allocate memory during processing of typical inputs, and thus
>> shouldn't be used in cases like dm-crypt where memory allocation
>> failures aren't accep
On 7/16/2020 2:53 PM, Herbert Xu wrote:
> On Thu, Jul 16, 2020 at 01:35:51PM +0300, Horia Geantă wrote:
>>
>> This patch set adds support only for some AES-based algorithms.
>> However, going further the plan is to add all keyed algorithms
>> supported by caam.
>>
On 7/16/2020 10:36 AM, Herbert Xu wrote:
> On Mon, Jul 13, 2020 at 01:05:36AM +0300, Iuliana Prodan wrote:
>> Tagged keys are keys that contain metadata indicating what
>> they are and how to handle them using tag_object API.
>>
>> Add support, for tagged keys, to skcipher algorithms by
>> adding n
> - retrieve metadata: get tag object header configuration, black key
> configuration or tag object data.
>
> This API expects that the object (the actual data) from a tag object
> to be a buffer (defined by address and size).
>
> Signed-off-by: Franck LENORMAND
Signed-off-b
https://lore.kernel.org/linux-crypto/20200702101947.682-1-a...@kernel.org
Acked-by: Horia Geantă
Horia
imx6sl SoC")
Signed-off-by: Horia Geantă
---
arch/arm/boot/dts/imx6sl.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 1c7180f28539..91a8c54d5e11 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/
Add node for the RNGB block.
Signed-off-by: Horia Geantă
---
arch/arm/boot/dts/imx6sll.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
index fb5d3bc50c6b..0b622201a1f3 100644
--- a/arch/arm/boot/dts/imx6sll.dtsi
with "fsl,imx25-rngb"
-collected Reviewed-by
v2
-update rngb DT binding with compatible strings for i.MX6 SoCs
Horia Geantă (5):
dt-bindings: rng: add RNGB compatibles for i.MX6 SoCs
ARM: dts: imx6sl: fix rng node
ARM: dts: imx6sll: add rng
ARM: dts: imx6ull: add rng
hwrng: imx
) crypto accelerator and this block and RNGB
are independent.
Signed-off-by: Horia Geantă
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/rng/imx-rng.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/rng/imx-rng.txt
b/Documentation/devicet
i.MX6 SL, SLL, ULL, ULZ SoCs have an RNGB block.
Since imx-rngc driver supports also rngb,
let's enable it for these SoCs too.
Signed-off-by: Horia Geantă
Reviewed-by: Martin Kaiser
Reviewed-by: Marco Felsch
---
drivers/char/hw_random/Kconfig | 2 +-
1 file changed, 1 insertion(
Add node for the RNGB block.
Signed-off-by: Horia Geantă
Reviewed-by: Marco Felsch
---
arch/arm/boot/dts/imx6ull.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
index fcde7f77ae42..9bf67490ac49 100644
--- a/arch
On 7/14/2020 3:48 PM, Arnd Bergmann wrote:
> On Tue, Jul 14, 2020 at 2:39 PM Horia Geantă wrote:
>> diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
>> index 8478eb757f3c..98f95a09ce55 100644
>> --- a/drivers/char/hw_random/Kconfig
>> +
imx6sl SoC")
Signed-off-by: Horia Geantă
---
arch/arm/boot/dts/imx6sl.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 1c7180f28539..91a8c54d5e11 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/
i.MX6 SL, SLL, ULL, ULZ SoCs have an RNGB block.
Since imx-rngc driver supports also rngb,
let's enable it for these SoCs too.
Signed-off-by: Horia Geantă
Reviewed-by: Martin Kaiser
Reviewed-by: Marco Felsch
---
drivers/char/hw_random/Kconfig| 2 +-
drivers/char/hw_random/imx-rngc.
Add node for the RNGB block.
Signed-off-by: Horia Geantă
Reviewed-by: Marco Felsch
---
arch/arm/boot/dts/imx6ull.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
index fcde7f77ae42..9bf67490ac49 100644
--- a/arch
) crypto accelerator and this block and RNGB
are independent.
Signed-off-by: Horia Geantă
---
Documentation/devicetree/bindings/rng/imx-rng.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/rng/imx-rng.txt
b/Documentation/devicetree/bindings/r
2
-update rngb DT binding with compatible strings for i.MX6 SoCs
Horia Geantă (5):
dt-bindings: rng: add RNGB compatibles for i.MX6 SoCs
ARM: dts: imx6sl: fix rng node
ARM: dts: imx6sll: add rng
ARM: dts: imx6ull: add rng
hwrng: imx-rngc: enable driver for i.MX6
Documentation/devicetre
Add node for the RNGB block.
Signed-off-by: Horia Geantă
---
arch/arm/boot/dts/imx6sll.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
index fb5d3bc50c6b..0b622201a1f3 100644
--- a/arch/arm/boot/dts/imx6sll.dtsi
On 7/14/2020 3:03 AM, Rob Herring wrote:
> On Sun, Jun 21, 2020 at 05:56:54PM +0300, Horia Geantă wrote:
>> RNGB block is found in some i.MX6 SoCs - 6SL, 6SLL, 6ULL, 6ULZ.
>> Add corresponding compatible strings.
>>
>> Note:
>>
>> Several NXP SoC from Q
On 7/13/2020 7:01 PM, Eric Biggers wrote:
> On Mon, Jul 13, 2020 at 06:49:00PM +0300, Horia Geantă wrote:
>> On 7/1/2020 7:52 AM, Eric Biggers wrote:
>>> From: Mikulas Patocka
>>>
>>> Set the flag CRYPTO_ALG_ALLOCATES_MEMORY in the crypto drivers that
>
On 7/1/2020 7:52 AM, Eric Biggers wrote:
> From: Mikulas Patocka
>
> Set the flag CRYPTO_ALG_ALLOCATES_MEMORY in the crypto drivers that
> allocate memory.
>
Quite a few drivers are impacted.
I wonder what's the proper way to address the memory allocation.
Herbert mentioned setting up reqsize:
On 7/9/2020 3:47 AM, Herbert Xu wrote:
> On Wed, Jul 08, 2020 at 07:24:08PM +0300, Horia Geantă wrote:
>>
>> I think the commit message should be updated to reflect this logic:
>> indeed, caam's implementation of ecb(arc4) is broken,
>> but instead of fixing it,
On 7/6/2020 4:43 PM, Ard Biesheuvel wrote:
> On Sun, 5 Jul 2020 at 22:11, Horia Geantă wrote:
>>
>> On 7/2/2020 7:36 AM, Herbert Xu wrote:
>>> The arc4 algorithm requires storing state in the request context
>>> in order to allow more than one encrypt/decrypt op
On 7/2/2020 7:36 AM, Herbert Xu wrote:
> The arc4 algorithm requires storing state in the request context
> in order to allow more than one encrypt/decrypt operation. As this
> driver does not seem to do that, it means that using it for more
> than one operation is broken.
>
The fact that smth. i
ating an ordinary skcipher
> as the fallback, and invoke it with the completion routine that was given
> to the outer request.
>
> Signed-off-by: Ard Biesheuvel
Reviewed-by: Horia Geantă
Thanks,
Horia
by allocating an ordinary skcipher
> as the fallback, and invoke it with the completion routine that was given
> to the outer request.
>
> Signed-off-by: Ard Biesheuvel
Reviewed-by: Horia Geantă
Thanks,
Horia
imx6sl SoC")
Signed-off-by: Horia Geantă
---
arch/arm/boot/dts/imx6sl.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 911d8cf77f2c..0339a46fa71c 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/
Add node for the RNGB block.
Signed-off-by: Horia Geantă
---
arch/arm/boot/dts/imx6ull.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
index fcde7f77ae42..9bf67490ac49 100644
--- a/arch/arm/boot/dts/imx6ull.dtsi
Add node for the RNGB block.
Signed-off-by: Horia Geantă
---
arch/arm/boot/dts/imx6sll.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
index edd3abb9a9f1..1c5dbccca013 100644
--- a/arch/arm/boot/dts/imx6sll.dtsi
i.MX6 SL, SLL, ULL, ULZ SoCs have an RNGB block.
Since imx-rngc driver supports also rngb,
let's enable it for these SoCs too.
Signed-off-by: Horia Geantă
---
drivers/char/hw_random/Kconfig| 2 +-
drivers/char/hw_random/imx-rngc.c | 3 +++
2 files changed, 4 insertions(+), 1 del
) crypto accelerator and this block and RNGB
are independent.
Signed-off-by: Horia Geantă
---
Documentation/devicetree/bindings/rng/imx-rng.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/rng/imx-rng.txt
b/Documentation/devicetree/bindings/r
nternally relying on
RNGB as source of randomness.
On the other hand, the i.MX6 SoCs with RNGB have a DCP
(Data Co-Processor) crypto accelerator and this block and RNGB
are independent.
Changelog:
-update rngb DT binding with compatible strings for i.MX6 SoCs
Horia Geantă (5):
dt-bindings: rng
On 6/20/2020 12:49 AM, Fabio Estevam wrote:
> On Fri, Jun 19, 2020 at 6:46 PM Fabio Estevam wrote:
>
>> If in the future more SoCs will use this IP, then we will need to keep
>> extending this list over and over again.
>>
>> Maybe you could use:
>>
>> depends on MACH_IMX || COMPILE_TEST
>
> MACH
Add node for the RNGB block.
Signed-off-by: Horia Geantă
---
arch/arm/boot/dts/imx6ull.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
index fcde7f77ae42..70cc098adeee 100644
--- a/arch/arm/boot/dts/imx6ull.dtsi
i.MX6 SL, SLL, ULL, ULZ SoCs have an RNGB block.
Since imx-rngc driver supports also rngb,
let's enable it for these SoCs too.
Signed-off-by: Horia Geantă
---
drivers/char/hw_random/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/char/hw_random/Kcon
Add node for the RNGB block.
Signed-off-by: Horia Geantă
---
arch/arm/boot/dts/imx6sll.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
index edd3abb9a9f1..e634cd45086b 100644
--- a/arch/arm/boot/dts/imx6sll.dtsi
;s tightly related to
the caam "job ring" interface.
Horia Geantă (4):
ARM: dts: imx6sl: fix rng node
ARM: dts: imx6sll: add rng
ARM: dts: imx6ull: add rng
hwrng: imx-rngc: enable driver for i.MX6
arch/arm/boot/dts/imx6sl.dtsi | 2 ++
arch/arm/boot/dts/imx6sll.dtsi | 7 ++
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