From: Igal Liberman <ig...@marvell.com>

When enable_single_wr is not enabled, the DSE will only write those
parts of a result descriptor that need updating, which means a final
result descriptor will be written in 2 or 3 smaller transfers.
When enable_single_wr is enabled the DSE will combine these 2-3
updates into one large write transfer, generally improving performance.

Signed-off-by: Igal Liberman <ig...@marvell.com>
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
 drivers/crypto/inside-secure/safexcel.c | 1 +
 drivers/crypto/inside-secure/safexcel.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/crypto/inside-secure/safexcel.c 
b/drivers/crypto/inside-secure/safexcel.c
index 99755fc1a161..658b307c6a11 100644
--- a/drivers/crypto/inside-secure/safexcel.c
+++ b/drivers/crypto/inside-secure/safexcel.c
@@ -329,6 +329,7 @@ static int safexcel_hw_init(struct safexcel_crypto_priv 
*priv)
        val = EIP197_HIA_DSE_CFG_DIS_DEBUG;
        val |= EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(7) | 
EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(8);
        val |= EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(WR_CACHE_3BITS);
+       val |= EIP197_HIA_DSE_CFG_EN_SINGLE_WR;
        writel(val, priv->base + EIP197_HIA_DSE_CFG);
 
        /* Leave the DSE threads reset state */
diff --git a/drivers/crypto/inside-secure/safexcel.h 
b/drivers/crypto/inside-secure/safexcel.h
index 0328a9314b90..b8a81c568c99 100644
--- a/drivers/crypto/inside-secure/safexcel.h
+++ b/drivers/crypto/inside-secure/safexcel.h
@@ -143,6 +143,7 @@
 #define EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(n)  (((n) & 0x7) << 20)
 #define EIP197_HIA_DxE_CFG_MAX_CTRL_SIZE(n)    ((n) << 24)
 #define EIP197_HIA_DFE_CFG_DIS_DEBUG           (BIT(31) | BIT(29))
+#define EIP197_HIA_DSE_CFG_EN_SINGLE_WR                BIT(29)
 #define EIP197_HIA_DSE_CFG_DIS_DEBUG           BIT(31)
 
 /* EIP197_HIA_DFE/DSE_THR_CTRL */
-- 
2.9.4

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