Re: [PATCH v2 1/4] dt-bindings: rng: Northstar Plus SoC rng bindings

On Wed, Jun 01, 2016 at 08:34:11PM +0530, Yendapally Reddy Dhananjaya Reddy wrote: > On Wed, Jun 1, 2016 at 8:17 PM, Rob Herring wrote: > > On Fri, May 27, 2016 at 06:10:38AM -0400, Yendapally Reddy Dhananjaya Reddy > > wrote: > >> Document the bindings used by Northstar

Re: [PATCH 02/28] crypto: omap-sham: Don't idle/start SHA device between Encrypt operations

On 06/01/2016 04:53 AM, Grygorii Strashko wrote: On 06/01/2016 11:56 AM, Tero Kristo wrote: From: Lokesh Vutla Calling runtime PM API for every block causes serious perf hit to crypto operations that are done on a long buffer. As crypto is performed on a page boundary,

[PATCH] crypto: skcipher - remove unused header cpumask.h

Remove unused header cpumask.h from crypto/ablkcipher.c. Signed-off-by: Geliang Tang --- crypto/ablkcipher.c | 1 - 1 file changed, 1 deletion(-) diff --git a/crypto/ablkcipher.c b/crypto/ablkcipher.c index e5b5721..6b80516 100644 --- a/crypto/ablkcipher.c +++

Re: (none)

On Wed, Jun 01, 2016 at 02:59:21AM -0400, Jeffrey Walton wrote: > > $ cat /proc/modules | egrep -i '(via|padlock|rng)' > padlock_sha 16384 0 - Live 0x > padlock_aes 16384 0 - Live 0x > via_cputemp 16384 0 - Live 0x > hwmon_vid 16384 1 via_cputemp, Live 0x > via_rng

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Am Mittwoch, 1. Juni 2016, 02:59:21 schrieb Jeffrey Walton: Hi Jeffrey, > On Wed, Jun 1, 2016 at 2:19 AM, Herbert Xu wrote: > > On Wed, Jun 01, 2016 at 07:53:38AM +0200, Stephan Mueller wrote: > >> I thought via-rng.c covers the VIA Padlock RNG? > > > > Indeed,

Re: (none)

On Wed, Jun 01, 2016 at 07:53:38AM +0200, Stephan Mueller wrote: > > I thought via-rng.c covers the VIA Padlock RNG? Indeed, you're quite right. In that case Jeffrey was the via-rng driver loaded? Thanks, -- Email: Herbert Xu Home Page:

Re: (none)

On Wed, Jun 1, 2016 at 2:19 AM, Herbert Xu wrote: > On Wed, Jun 01, 2016 at 07:53:38AM +0200, Stephan Mueller wrote: >> >> I thought via-rng.c covers the VIA Padlock RNG? > > Indeed, you're quite right. In that case Jeffrey was the via-rng > driver loaded? $ cat

[PATCH 00/28] crypto: omap fixes / support additions

Hi, This series adds support for crypto hardware accelerators on TI DRA7xx and AM43xx SoCs, and fixes a number of bugs in the existing codebase. This series also addresses performance issues with the AES / SHA accelerators, doing some optimizations on these. Patch #7 and #13 are generic crypto

[PATCH 14/28] crypto: omap-aes: fix crypto engine initialization order

The crypto engine must be initialized before registering algorithms, otherwise the test manager will crash as it attempts to execute tests for the algos while they are being registered. Fixes: 0529900a01cb ("crypto: omap-aes - Support crypto engine framework") Signed-off-by: Tero Kristo

[PATCH 10/28] crypto: omap-aes - Fix enabling clocks

From: Lokesh Vutla Enable clocks for all cores before starting session. Driver has to pic the aes core dynamically based on the queue length. Signed-off-by: Lokesh Vutla --- drivers/crypto/omap-aes.c | 23 +++ 1 file changed, 7

[PATCH 15/28] crypto: omap-des: fix crypto engine initialization order

The crypto engine must be initialized before registering algorithms, otherwise the test manager will crash as it attempts to execute tests for the algos while they are being registered. Fixes: f1b77aaca85a ("crypto: omap-des - Integrate with the crypto engine framework") Signed-off-by: Tero

[PATCH 04/28] crypto: omap: do not call dmaengine_terminate_all

From: Lokesh Vutla The extra call to dmaengine_terminate_all is not needed, as the DMA is not running at this point. This improves performance slightly. Signed-off-by: Lokesh Vutla Signed-off-by: Tero Kristo ---

[PATCH 03/28] crypto: omap-sham: change queue size from 1 to 10

Change crypto queue size from 1 to 10 for omap SHA driver. This should allow clients to enqueue requests more effectively to avoid serializing whole crypto sequences, giving extra performance. Signed-off-by: Tero Kristo --- drivers/crypto/omap-sham.c | 2 +- 1 file changed, 1

[PATCH 13/28] crypto: engine: avoid unnecessary context switches

Crypto engine will now hi-jack the currently running thread for executing crypto functionality. Only if we are not running a thread (in interrupt context) the kthread will be scheduled. This will improve performance of crypto operations using crypto engine. Signed-off-by: Tero Kristo

[PATCH 07/28] crypto: ahash: increase the maximum allowed statesize

The statesize is used to determine the maximum size for saved ahash context. In some cases, this can be much larger than what is currently allocated for it, for example omap-sham driver uses a buffer size of PAGE_SIZE. Increase the statesize to accommodate this. Signed-off-by: Tero Kristo

[PATCH 09/28] crypto: omap-des: Fix support for unequal lengths

From: Lokesh Vutla For cases where total length of an input SGs is not same as length of the input data for encryption, omap-des driver crashes. This happens in the case when IPsec is trying to use omap-des driver. To avoid this, we copy all the pages from the input SG list

[PATCH 12/28] crypto: omap-aes: Add fallback support

From: Lokesh Vutla As setting up the DMA operations is quite costly, add software fallback support for requests smaller than 200 bytes. This change gives some 10% extra performance in ipsec use case. Signed-off-by: Lokesh Vutla Signed-off-by: Tero Kristo

[PATCH 05/28] crypto: omap-sham: set sw fallback to 240 bytes

From: Bin Liu Adds software fallback support for small crypto requests. In these cases, it is undesirable to use DMA, as setting it up itself is rather heavy operation. Gives about 40% extra performance in ipsec usecase. Signed-off-by: Bin Liu [t-kri...@ti.com:

[PATCH 08/28] crypto: omap-sham: implement context export/import APIs

Context export/import are now required for ahash algorithms due to required support in algif_hash. Implement these for OMAP SHA driver, saving and restoring the internal state of the driver. Signed-off-by: Tero Kristo --- drivers/crypto/omap-sham.c | 40

[PATCH 06/28] crypto: omap-sham: avoid executing tasklet where not needed

Some of the call paths of OMAP SHA driver can avoid executing the next step of the crypto queue under tasklet; instead, execute the next step directly via function call. This avoids a costly round-trip via the scheduler giving a slight performance boost. Signed-off-by: Tero Kristo

[PATCH 11/28] crypto: omap-aes: Add support for multiple cores

From: Lokesh Vutla Some SoCs like omap4/omap5/dra7 contain multiple AES crypto accelerator cores. Adapt the driver to support this. The driver picks the last used device from a list of AES devices. Signed-off-by: Lokesh Vutla [t-kri...@ti.com: forward

[PATCH 01/28] crypto: omap-aes: Fix registration of algorithms

From: Lokesh Vutla Algorithms can be registered only once. So skip registration of algorithms if already registered (i.e. in case we have two AES cores in the system.) Signed-off-by: Lokesh Vutla Signed-off-by: Tero Kristo ---

[PATCH 18/28] ARM: DRA7: hwmod: Add data for SHA IP

From: Lokesh Vutla DRA7 SoC contains SHA crypto hardware accelerator. Add hwmod data for this IP so that it can be utilized by crypto frameworks. Signed-off-by: Lokesh Vutla Signed-off-by: Tero Kristo ---

[PATCH 27/28] ARM: dts: AM43xx: clk: Add RNG clk node

From: Lokesh Vutla Add clk node for RNG module. Signed-off-by: Lokesh Vutla --- arch/arm/boot/dts/am43xx-clocks.dtsi | 8 drivers/clk/ti/clk-43xx.c| 1 + 2 files changed, 9 insertions(+) diff --git

[PATCH 24/28] ARM: dts: DRA7: Add DT nodes for AES IP

From: Joel Fernandes DRA7 SoC has the same AES IP as OMAP4. Add DT entries for both AES cores. Signed-off-by: Joel Fernandes Signed-off-by: Lokesh Vutla [t-kri...@ti.com: squashed in the change to use EDMA, squashed in support

[PATCH 25/28] ARM: dts: DRA7: Add support for SHA IP

From: Lokesh Vutla DRA7 SoC has the same SHA IP as OMAP5. Add DT entry for the same. Signed-off-by: Lokesh Vutla [t-kri...@ti.com: changed SHA to use EDMA instead of SDMA] Signed-off-by: Tero Kristo --- arch/arm/boot/dts/dra7.dtsi | 11

[PATCH 22/28] ARM: AMx3xx: hwmod: Add data for RNG

From: Lokesh Vutla Hardware random number generator is present in both AM33xx and AM43xx SoC's. So moving the hwmod data to common data. Signed-off-by: Lokesh Vutla Signed-off-by: Tero Kristo ---

[PATCH 23/28] ARM: dts: DRA7: Add DT node for DES IP

From: Joel Fernandes DRA7xx SoCs have a DES3DES IP. Add DT data for the same. Signed-off-by: Joel Fernandes --- arch/arm/boot/dts/dra7.dtsi | 11 +++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi

[PATCH 19/28] ARM: DRA7: hwmod: Add data for RNG IP

From: Joel Fernandes DRA7 SoC contains hardware random number generator. Add hwmod data for this IP so that it can be utilized. Signed-off-by: Joel Fernandes Signed-off-by: Lokesh Vutla [t-kri...@ti.com: squashed the RNG hwmod IP flag fixes from

[PATCH 28/28] ARM: dts: AM43xx: Add node for RNG

From: Lokesh Vutla Adding DT node for hardware random number generator. Signed-off-by: Lokesh Vutla --- arch/arm/boot/dts/am4372.dtsi | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/am4372.dtsi

[PATCH 20/28] ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP only

From: Joel Fernandes Using HWSUP for l4sec clock domain is causing warnings in HWMOD code for DRA7. Based on some observations, once the clock domain goes into an IDLE state (because of no activity etc), the IDLEST for the module goes to '0x2' value which means Interface IDLE

[PATCH 26/28] ARM: dts: DRA7: Add DT node for RNG IP

From: Lokesh Vutla Adding dt node for hardware random number generator IP. Signed-off-by: Lokesh Vutla --- arch/arm/boot/dts/dra7.dtsi | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi

[PATCH 17/28] ARM: DRA7: hwmod: Add data for AES IP

From: Joel Fernandes DRA7 SoC contains AES crypto hardware accelerator. Add hwmod data for this IP so that it can be utilized by crypto frameworks. Signed-off-by: Joel Fernandes Signed-off-by: Lokesh Vutla [t-kri...@ti.com: squash in support for

Re: [PATCH 02/28] crypto: omap-sham: Don't idle/start SHA device between Encrypt operations

On 06/01/2016 11:56 AM, Tero Kristo wrote: From: Lokesh Vutla Calling runtime PM API for every block causes serious perf hit to crypto operations that are done on a long buffer. As crypto is performed on a page boundary, encrypting large buffers can cause a series of crypto

[PATCH v4] Bluetooth: convert smp and selftest to crypto kpp API

* Convert both smp and selftest to crypto kpp API * Remove module ecc as not more required * Add ecdh_helper functions for wrapping kpp async calls Signed-off-by: Salvatore Benedetto --- Patch based on https://patchwork.kernel.org/patch/9145037/ Changes from

[PATCH 16/28] ARM: DRA7: hwmod: Add data for DES IP

From: Joel Fernandes DRA7 SoC contains DES crypto hardware accelerator. Add hwmod data for this IP so that it can be utilized by crypto frameworks. Signed-off-by: Joel Fernandes Signed-off-by: Lokesh Vutla Signed-off-by: Tero Kristo

Re: [PATCH v2 1/4] dt-bindings: rng: Northstar Plus SoC rng bindings

On Fri, May 27, 2016 at 06:10:38AM -0400, Yendapally Reddy Dhananjaya Reddy wrote: > Document the bindings used by Northstar Plus(NSP) SoC random number > generator. > > Signed-off-by: Yendapally Reddy Dhananjaya Reddy > > Acked-by: Eric Anholt

Re: [PATCH v2 1/4] dt-bindings: rng: Northstar Plus SoC rng bindings

On Wed, Jun 1, 2016 at 8:17 PM, Rob Herring wrote: > On Fri, May 27, 2016 at 06:10:38AM -0400, Yendapally Reddy Dhananjaya Reddy > wrote: >> Document the bindings used by Northstar Plus(NSP) SoC random number >> generator. >> >> Signed-off-by: Yendapally Reddy Dhananjaya Reddy