On Mon, Sep 09, 2019 at 03:38:39PM +0300, Tomer Maimon wrote:
> Added device tree binding documentation for Nuvoton BMC
> NPCM Random Number Generator (RNG).
>
> Signed-off-by: Tomer Maimon
> ---
> .../bindings/rng/nuvoton,npcm-rng.txt | 17 +
> 1 file changed, 17 inser
On Fri, Aug 30, 2019 at 10:05 PM Andrey Smirnov
wrote:
>
> Add node for CAAM - Cryptographic Acceleration and Assurance Module.
>
> Signed-off-by: Horia Geantă
> Signed-off-by: Andrey Smirnov
The patch itself looks good to me.
Acked-by: Li Yang
> Cc: Cory Tusar
> Cc: Chris Healy
> Cc: Luca
On Mon, Sep 09, 2019 at 03:38:40PM +0300, Tomer Maimon wrote:
> Add Nuvoton NPCM BMC Random Number Generator(RNG) driver.
>
> Signed-off-by: Tomer Maimon
> ---
> drivers/char/hw_random/Kconfig| 13 ++
> drivers/char/hw_random/Makefile | 1 +
> drivers/char/hw_random/npcm-rng.c | 203 +++
On Tue, Sep 10, 2019 at 01:52:35PM +0300, Tomer Maimon wrote:
> Hi Daniel,
>
> Thanks for your prompt reply,
>
>
>
> On Mon, 9 Sep 2019 at 18:10, Daniel Thompson
> wrote:
>
> > On Mon, Sep 09, 2019 at 05:31:30PM +0300, Tomer Maimon wrote:
> > > Hi Daniel,
> > >
> > > appreciate your comments
On Tue, Sep 10, 2019 at 02:55:44PM +0300, Tomer Maimon wrote:
> Hi Daniel,
>
> Sorry but I have probably miss it, thanks a lot for your comment
>
> On Tue, 10 Sep 2019 at 13:25, Daniel Thompson
> wrote:
>
> > On Mon, Sep 09, 2019 at 03:38:39PM +0300, Tomer Maimon wrote:
> > > Added device tree
Herbert, Eric,
I noticed some interesting behavior from the crypto manager when
dealing with a fallback cipher situation.
I'm allocating a fallback (AEAD) cipher to handle some corner cases
my HW cannot handle, but I noticed that the fallback itself is being
tested when I allocate it (or so it s
On Tue, Sep 10, 2019 at 12:50:04PM +, Pascal Van Leeuwen wrote:
>
> I'm allocating a fallback (AEAD) cipher to handle some corner cases
> my HW cannot handle, but I noticed that the fallback itself is being
> tested when I allocate it (or so it seems) and if the fallback itself
> fails on some
> -Original Message-
> From: Herbert Xu
> Sent: Tuesday, September 10, 2019 2:59 PM
> To: Pascal Van Leeuwen
> Cc: linux-crypto@vger.kernel.org; Eric Biggers
> Subject: Re: Interesting crypto manager behavior
>
> On Tue, Sep 10, 2019 at 12:50:04PM +, Pascal Van Leeuwen wrote:
> >
> -Original Message-
> From: linux-crypto-ow...@vger.kernel.org
> On Behalf
> Of Pascal Van Leeuwen
> Sent: Tuesday, September 10, 2019 3:10 PM
> To: Herbert Xu
> Cc: linux-crypto@vger.kernel.org; Eric Biggers
> Subject: RE: Interesting crypto manager behavior
>
>
>
> > -Original
Hi all,
In commit
f2ef960231d7 ("crypto: caam - dispose of IRQ mapping only after IRQ is freed")
Fixes tag
Fixes: f314f12db65c ("crypto: caam - convert caam_jr_init() to use devres")
has these problem(s):
- Target SHA1 does not exist
Did you mean
Fixes: a6c4194ead00 ("crypto: caam - c
Extend driver support with chacha20, rfc7539(chacha20,poly1305) and
rfc7539esp(chacha20,poly1305) ciphers.
The patchset has been tested with the eip197c_iesb and eip197c_iewxkbc
configurations on the Xilinx VCU118 development board, including the
crypto extra tests.
Note that this patchset applies
This patch adds support for the Chacha20-Poly1305 cipher suite.
It adds both the basic rfc7539(chacha20,poly1305) as well as the
rfc7539esp(chacha20,poly1305) variant for IPsec ESP acceleration.
Signed-off-by: Pascal van Leeuwen
---
drivers/crypto/inside-secure/safexcel.c| 2 +
drivers
Added support for the CHACHA20 skcipher algorithm.
Tested on an eip197c-iesb configuration in the Xilinx VCU118 devboard,
passes all testmgr vectors plus the extra fuzzing tests.
Signed-off-by: Pascal van Leeuwen
---
drivers/crypto/inside-secure/safexcel.c| 1 +
drivers/crypto/inside-se
On Mon, Sep 09, 2019 at 01:16:48PM +0100, James Bottomley wrote:
> Link to previous cover letter:
>
> https://lore.kernel.org/linux-integrity/1540193596.3202.7.ca...@hansenpartnership.com/
>
> This is marked v6 instead of v5 because I did a v5 after feedback on v4
> but didn't get around to posti
On Tue, 2019-09-10 at 17:21 +0100, Jarkko Sakkinen wrote:
> On Mon, Sep 09, 2019 at 01:16:48PM +0100, James Bottomley wrote:
> > Link to previous cover letter:
> >
> > https://lore.kernel.org/linux-integrity/1540193596.3202.7.camel@Han
> > senPartnership.com/
> >
> > This is marked v6 instead of
*ping*
Anyone?
-Original Message-
From: linux-crypto-ow...@vger.kernel.org
On Behalf Of Gary R Hook
Sent: Thursday, August 15, 2019 5:32 PM
To: linux-crypto@vger.kernel.org
Subject: Crypto driver callback problem
Context:
We've run into a possible locking issue when using the AMD CCP d
And an apology for a ping using the wrong mail handler, and the top post...
Would love to know if this has gotten any cycles.
On 8/15/19 5:31 PM, Gary R Hook wrote:
> Context:
> We've run into a possible locking issue when using the AMD CCP device
> for crypto offload, with the new extra tests, a
Hi Pascal,
On Tue, Sep 10, 2019 at 04:38:12PM +0200, Pascal van Leeuwen wrote:
>
> @@ -112,7 +123,7 @@ static void safexcel_cipher_token(struct
> safexcel_cipher_ctx *ctx, u8 *iv,
> block_sz = DES3_EDE_BLOCK_SIZE;
> cdesc->control_data.options |=
> E
> -Original Message-
> From: Antoine Tenart
> Sent: Tuesday, September 10, 2019 7:33 PM
> To: Pascal van Leeuwen
> Cc: linux-crypto@vger.kernel.org; antoine.ten...@bootlin.com;
> herb...@gondor.apana.org.au;
> da...@davemloft.net; Pascal Van Leeuwen
> Subject: Re: [PATCH 1/2] crypto: in
On September 9, 2019 around 7:40AM in somet timezone, Tomer Maimon wrote:
>+#define NPCM_RNG_TIMEOUT_USEC 2
>+#define NPCM_RNG_POLL_USEC1000
...
>+static int npcm_rng_init(struct hwrng *rng)
>+{
>+ struct npcm_rng *priv = to_npcm_rng(rng);
>+ u32 val;
>+
>+ val = readl(priv
To improve performance on cores with deep pipelines such as ThunderX2,
reimplement gcm(aes) using a 4-way interleave rather than the 2-way
interleave we use currently.
This comes down to a complete rewrite of the GCM part of the combined
GCM/GHASH driver, and instead of interleaving two invocation
This series reimplements gcm(aes) for arm64 systems that support the
AES and 64x64->128 PMULL/PMULL2 instructions. Patch #1 adds a test
case and patch #2 updates the driver.
Ard Biesheuvel (2):
crypto: testmgr - add another gcm(aes) testcase
crypto: arm64/gcm-ce - implement 4 way interleave
Add an additional gcm(aes) test case that triggers the code path in
the new arm64 driver that deals with tail blocks whose size is not
a multiple of the block size, and where the size of the preceding
input is a multiple of 64 bytes.
Signed-off-by: Ard Biesheuvel
---
crypto/testmgr.h | 192 +
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