Re: [PATCH v5 0/5] Thermal: Support for hardware-tracked trip points

On 二, 2016-06-21 at 09:42 +0800, Caesar Wang wrote: > Do you have other ideas for the following patches? :-)  > Even if only took two weeks feel after a long time. > > 9157919 New  [v5,1/5] thermal: Add support for hardware- > tracked trip points > 9157917 New  [v5,2/5] thermal:

Re: [PATCH v5 1/5] thermal: Add support for hardware-tracked trip points

On 一, 2016-06-06 at 19:44 +0800, Caesar Wang wrote: > From: Sascha Hauer > > This adds support for hardware-tracked trip points to the device tree > thermal sensor framework. > > The framework supports an arbitrary number of trip points. Whenever > the current

[PATCH v7 0/9] x86/mm: memory area address KASLR

This is v7 of Thomas Garnier's KASLR for memory areas (physical memory mapping, vmalloc, vmemmap). It expects to be applied on top of the x86/boot tip. The current implementation of KASLR randomizes only the base address of the kernel and its modules. Research was published showing that static

[PATCH v7 6/9] x86/mm: Enable KASLR for physical mapping memory region (x86_64)

From: Thomas Garnier Add the physical mapping in the list of randomized memory regions. The physical memory mapping holds most allocations from boot and heap allocators. Knowing the base address and physical memory size, an attacker can deduce the PDE virtual address for

[PATCH v7 7/9] x86/mm: Enable KASLR for vmalloc memory region (x86_64)

From: Thomas Garnier Add vmalloc in the list of randomized memory regions. The vmalloc memory region contains the allocation made through the vmalloc API. The allocations are done sequentially to prevent fragmentation and each allocation address can easily be deduced

[PATCH v7 2/9] x86/mm: Update physical mapping variable names (x86_64)

From: Thomas Garnier Change the variable names on kernel_physical_mapping_init and related functions to correctly reflect physical and virtual memory addresses. Also add comments on each function to describe usage and alignment constraints. Signed-off-by: Thomas Garnier

[PATCH v7 4/9] x86/mm: Separate variable for trampoline PGD (x86_64)

From: Thomas Garnier Use a separate global variable to define the trampoline PGD used to start other processors. This change will allow KALSR memory randomization to change the trampoline PGD to be correctly aligned with physical memory. Signed-off-by: Thomas Garnier

[PATCH v7 1/9] x86/mm: Refactor KASLR entropy functions

From: Thomas Garnier Move the KASLR entropy functions into arch/x86/lib to be used in early kernel boot for KASLR memory randomization. Signed-off-by: Thomas Garnier Signed-off-by: Kees Cook --- arch/x86/boot/compressed/kaslr.c

[PATCH v7 8/9] x86/mm: Enable KASLR for vmemmap memory region (x86_64)

From: Thomas Garnier Add vmemmap in the list of randomized memory regions. The vmemmap region holds a representation of the physical memory (through a struct page array). An attacker could use this region to disclose the kernel memory layout (walking the page linked list).

Re: [PATCH v4 0/1] pstore/ram: add Device Tree bindings

On Tue, Jun 14, 2016 at 09:40:47PM -0700, Kees Cook wrote: > On Tue, Jun 14, 2016 at 2:59 PM, Rob Herring wrote: > > On Fri, Jun 10, 2016 at 03:50:58PM -0700, Kees Cook wrote: > >> This is a "v4" of Greg Hackmann's DT bindings for ramoops. This is > >> what I'm going to land in

Re: [PATCHv4 4/7] Documentation: dt: socfpga: Add Arria10 Ethernet binding

On 06/21/2016 10:48 AM, Rob Herring wrote: On Tue, Jun 21, 2016 at 9:46 AM, Thor Thayer wrote: Hi Rob, On 06/21/2016 08:33 AM, Rob Herring wrote: On Mon, Jun 20, 2016 at 09:50:49AM -0500, ttha...@opensource.altera.com wrote: From: Thor Thayer

Re: [PATCH 08/19] arm64: introduce is_a32_task and is_a32_thread (for AArch32 compat)

On Tuesday, June 21, 2016 1:34:59 PM CEST Andreas Schwab wrote: > "Zhangjian (Bamvor)" writes: > > >> @@ -78,9 +79,9 @@ > >> > >> #ifdef CONFIG_COMPAT > >> #define TASK_SIZE_32 UL(0x1) > >> -#define TASK_SIZE

Re: [PATCHv4 4/7] Documentation: dt: socfpga: Add Arria10 Ethernet binding

On Tue, Jun 21, 2016 at 9:46 AM, Thor Thayer wrote: > Hi Rob, > > > On 06/21/2016 08:33 AM, Rob Herring wrote: >> >> On Mon, Jun 20, 2016 at 09:50:49AM -0500, ttha...@opensource.altera.com >> wrote: >>> >>> From: Thor Thayer >>> >>>

Re: [PATCH v3 2/7] leds: documentation: 'ide-disk' to 'disk-activity'

On Thu, Jun 09, 2016 at 12:29:37AM +0200, Stephan Linz wrote: > Cc: Joseph Jezak > Cc: Nico Macrionitis > Cc: Jörg Sommer > Signed-off-by: Stephan Linz > --- > Documentation/devicetree/bindings/leds/common.txt| 2

Re: [PATCHv4 4/7] Documentation: dt: socfpga: Add Arria10 Ethernet binding

Hi Rob, On 06/21/2016 08:33 AM, Rob Herring wrote: On Mon, Jun 20, 2016 at 09:50:49AM -0500, ttha...@opensource.altera.com wrote: From: Thor Thayer Add the device tree bindings needed to support the Altera Ethernet FIFO buffers on the Arria10 chip.

Re: [PATCHv4 4/7] Documentation: dt: socfpga: Add Arria10 Ethernet binding

On Mon, Jun 20, 2016 at 09:50:49AM -0500, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Add the device tree bindings needed to support the Altera Ethernet > FIFO buffers on the Arria10 chip. > > Signed-off-by: Thor Thayer

Re: [PATCH v2 0/7] Documentation: convert DocBook gpu.tmpl to reStructuredText

On Tue, Jun 21, 2016 at 02:48:56PM +0300, Jani Nikula wrote: > Take two of [1], see the cover letter there. > > I've renamed drm-userland-interfaces.rst to drm-uapi.rst and added a > further split-up patch of drm internals, extracting mm, kms and kms > helpers to separate documents. All applied

Re: [PATCH 08/19] arm64: introduce is_a32_task and is_a32_thread (for AArch32 compat)

"Zhangjian (Bamvor)" writes: >> @@ -78,9 +79,9 @@ >> >> #ifdef CONFIG_COMPAT >> #define TASK_SIZE_32 UL(0x1) >> -#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \ >> +#define TASK_SIZE (is_compat_task() ? \

[PATCH v2 3/7] MAINTAINERS: add Documentation/gpu and Documentation/gpu/i915.rst

We'll want to keep an eye on what's going on in these files. Signed-off-by: Jani Nikula --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index cb88f724e07c..ce9c23dd02c6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3857,6

[PATCH v2 4/7] Documentation/gpu: use recommended order of heading markers

While splitting the document up, the headings "shifted" from what pandoc generated. Use the following order for headings for consistency: == Document title == First = Second -- Third ~ Leave the lower level headings as they are; I think those are less

[PATCH v2 0/7] Documentation: convert DocBook gpu.tmpl to reStructuredText

Take two of [1], see the cover letter there. I've renamed drm-userland-interfaces.rst to drm-uapi.rst and added a further split-up patch of drm internals, extracting mm, kms and kms helpers to separate documents. BR, Jani. [1] http://mid.gmane.org/cover.1466434348.git.jani.nik...@intel.com

Re: [PATCH 08/19] arm64: introduce is_a32_task and is_a32_thread (for AArch32 compat)

Hi, On 2016/6/18 7:54, Yury Norov wrote: Based on patch of Andrew Pinski. This patch introduces is_a32_compat_task and is_a32_thread so it is easier to say this is a a32 specific thread or a generic compat thread/task. Corresponding functions are located in to avoid mess in headers. Some

Re: [RESEND PATCH 1/3] rfkill: Create "rfkill-airplane-mode" LED trigger

On Mon, 2016-06-13 at 23:21 +0200, Pavel Machek wrote: >  > (Actually, "::wifi" is super confusing, I'd expect that to be a led > that blinks when wifi is active.) Agree with that, yeah, that'd be confusing. > Well... "airplane" is quite confusing. I'd we use "rfkill" for > disabling radios, and

Re: [RESEND PATCH v2 1/4] PCI: Ignore resource_alignment if PCI_PROBE_ONLY was set\\

On 2016/6/21 10:16, Yongji Xie wrote: On 2016/6/21 9:43, Bjorn Helgaas wrote: On Thu, Jun 02, 2016 at 01:46:48PM +0800, Yongji Xie wrote: The resource_alignment will releases memory resources allocated by firmware so that kernel can reassign new resources later on. But this will cause the

Re: [RESEND PATCH v2 4/4] PCI: Add support for enforcing all MMIO BARs to be page aligned

On 2016/6/21 10:26, Bjorn Helgaas wrote: On Thu, Jun 02, 2016 at 01:46:51PM +0800, Yongji Xie wrote: When vfio passthrough a PCI device of which MMIO BARs are smaller than PAGE_SIZE, guest will not handle the mmio accesses to the BARs which leads to mmio emulations in host. This is because