Re: [PATCH 4/5] acpi/processor: Fix the return value of acpi_processor_ids_walk()

At 05/19/2018 11:06 PM, Thomas Gleixner wrote: On Tue, 20 Mar 2018, Dou Liyang wrote: ACPI driver should make sure all the processor IDs in their ACPI Namespace are unique for CPU hotplug. the driver performs a depth-first walk of the namespace tree and calls the acpi_processor_ids_walk().

Re: Documentation/translations: Italian

On Mon, 21 May 2018 22:54:18 +0200 Federico Vaga wrote: > I'm writing you because I would like to start an effort to translate the > Documentation in Italian. I would like also to express the idea of providing > guide lines for translations. Mi sembra un'ottima idea!

Documentation/translations: Italian

Hello, I'm writing you because I would like to start an effort to translate the Documentation in Italian. I would like also to express the idea of providing guide lines for translations. A looked a bit in the archive but I did not find anything about these two topics (Italian translation,

Re: [PATCH v5 3/5] i2c: i2c-qcom-geni: Add bus driver for the Qualcomm GENI I2C controller

Hi, On Fri, Mar 23, 2018 at 02:20:59PM -0600, Karthikeyan Ramasubramanian wrote: > This bus driver supports the GENI based i2c hardware controller in the > Qualcomm SOCs. The Qualcomm Generic Interface (GENI) is a programmable > module supporting a wide range of serial interfaces including I2C.

[v4 08/11] Documentation: hwmon: Add documents for PECI hwmon client drivers

This commit adds hwmon documents for PECI cputemp and dimmtemp drivers. Signed-off-by: Jae Hyun Yoo Reviewed-by: Haiyue Wang Reviewed-by: James Feist Reviewed-by: Vernon Mauery

[v4 02/11] Documentation: ioctl: Add ioctl numbers for PECI subsystem

This commit updates ioctl-number.txt to reflect ioctl numbers used by the PECI subsystem. Signed-off-by: Jae Hyun Yoo Cc: James Feist Cc: Jason M Biils Cc: Vernon Mauery

[PATCH v4 00/10] PECI device driver introduction

Introduction of the Platform Environment Control Interface (PECI) bus device driver. PECI is a one-wire bus interface that provides a communication channel between an Intel processor and chipset components to external monitoring or control devices. PECI is designed to support the following

Re: [PATCH 0/3] bpf: add boot parameters for sysctl knobs

On Mon, May 21, 2018 at 02:29:30PM +0200, Eugene Syromiatnikov wrote: > Hello. > > This patch set adds ability to set default values for > kernel.unprivileged_bpf_disable, net.core.bpf_jit_harden, > net.core.bpf_jit_kallsyms sysctl knobs as well as option to override > them via a boot-time kernel

[PATCH] Documentation: document hung_task_panic kernel parameter

From: Omar Sandoval This parameter has been around since commit e162b39a368f ("softlockup: decouple hung tasks check from softlockup detection") in 2009 but was never documented. Signed-off-by: Omar Sandoval --- Documentation/admin-guide/kernel-parameters.txt |

Re: [PATCH v5 3/5] i2c: i2c-qcom-geni: Add bus driver for the Qualcomm GENI I2C controller

Wolfram, On Fri, Mar 23, 2018 at 4:34 PM, Doug Anderson wrote: > Hi, > > On Fri, Mar 23, 2018 at 1:20 PM, Karthikeyan Ramasubramanian > wrote: >> This bus driver supports the GENI based i2c hardware controller in the >> Qualcomm SOCs. The Qualcomm

Re: [PATCH v2 0/7] mm: pages for hugetlb's overcommit may be able to charge to memcg

On 05/17/2018 09:27 PM, TSUKADA Koutaro wrote: > Thanks to Mike Kravetz for comment on the previous version patch. > > The purpose of this patch-set is to make it possible to control whether or > not to charge surplus hugetlb pages obtained by overcommitting to memory > cgroup. In the future, I

Re: [PATCH v8 1/6] cpuset: Enable cpuset controller in default hierarchy

On 05/21/2018 11:09 AM, Patrick Bellasi wrote: > On 21-May 09:55, Waiman Long wrote: > >> Changing cpuset.cpus will require searching for the all the tasks in >> the cpuset and change its cpu mask. > ... I'm wondering if that has to be the case. In principle there can > be a different solution

Re: [PATCH 0/3] docs/vm: transhuge: split userspace bits to admin-guide/mm

On Mon, 14 May 2018 11:13:37 +0300 Mike Rapoport wrote: > Here are minor updates to transparent hugepage docs. Except from minor > formatting and spelling updates, these patches re-arrange the transhuge.rst > so that userspace interface description will not be

Re: [PATCH v8 1/6] cpuset: Enable cpuset controller in default hierarchy

On 21-May 09:55, Waiman Long wrote: > On 05/21/2018 07:55 AM, Patrick Bellasi wrote: > > Hi Waiman! [...] > >> +Cpuset > >> +-- > >> + > >> +The "cpuset" controller provides a mechanism for constraining > >> +the CPU and memory node placement of tasks to only the resources > >> +specified in

Re: [PATCH v2 3/7] memcg: use compound_order rather than hpage_nr_pages

TSUKADA Koutaro writes: > On 2018/05/19 2:51, Punit Agrawal wrote: >> Punit Agrawal writes: >> >>> Tsukada-san, >>> >>> I am not familiar with memcg so can't comment about whether the patchset >>> is the right way to solve the problem outlined in the

Re: [PATCH v2 0/7] mm: pages for hugetlb's overcommit may be able to charge to memcg

Hi Tsukada, I was staring at memcg code to better understand your changes and had the below thought. TSUKADA Koutaro writes: [...] > In this patch-set, introduce the charge_surplus_huge_pages(boolean) to > struct hstate. If it is true, it charges to the memory cgroup to

Re: [PATCH v8 1/6] cpuset: Enable cpuset controller in default hierarchy

On 05/21/2018 07:55 AM, Patrick Bellasi wrote: > Hi Waiman! > > I've started looking at the possibility to move Android to use cgroups > v2 and the availability of the cpuset controller makes this even more > promising. > > I'll try to give a run to this series on Android, meanwhile I have > some

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

On Mon, May 21, 2018 at 4:10 PM, Mark Rutland wrote: > On Mon, May 21, 2018 at 11:37:12AM +0100, Mark Rutland wrote: >> Hi Ganapat, >> >> >> Sorry for the delay in replying; I was away most of last week. >> >> On Tue, May 15, 2018 at 04:03:19PM +0530, Ganapatrao Kulkarni

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

Hi Mark, On Mon, May 21, 2018 at 4:25 PM, Mark Rutland wrote: > On Sat, May 05, 2018 at 12:16:13AM +0530, Ganapatrao Kulkarni wrote: >> On Thu, Apr 26, 2018 at 4:29 PM, Mark Rutland wrote: >> > On Wed, Apr 25, 2018 at 02:30:47PM +0530, Ganapatrao

[PATCH 3/3] bpf: add ability to configure BPF JIT kallsyms export at the boot time

This patch introduces two configuration options, BPF_JIT_KALLSYMS_BOOTPARAM and BPF_JIT_KALLSYMS_BOOTPARAM_VALUE, that allow configuring the initial value of net.core.bpf_jit_kallsyms sysctl knob. This enables export of addresses of JIT'ed BPF programs that created during the early boot.

[PATCH 2/3] bpf: add ability to configure BPF JIT hardening via boot-time parameter

This patch introduces two configuration options, BPF_JIT_HARDEN_BOOTPARAM and BPF_JIT_HARDEN_BOOTPARAM_VALUE, that allow configuring the initial value of net.core.bpf_jit_harden sysctl knob, which is useful for enforcing JIT hardening during the early boot. Signed-off-by: Eugene Syromiatnikov

[PATCH 1/3] bpf: add ability to configure unprivileged BPF via boot-time parameter

This patch introduces two configuration options, UNPRIVILEGED_BPF_BOOTPARAM and UNPRIVILEGED_BPF_BOOTPARAM_VALUE, that allow configuring the initial value of kernel.unprivileged_bpf_disabled sysctl knob, which is useful for the cases when disabling unprivileged bpf() access during the early boot

[PATCH 0/3] bpf: add boot parameters for sysctl knobs

Hello. This patch set adds ability to set default values for kernel.unprivileged_bpf_disable, net.core.bpf_jit_harden, net.core.bpf_jit_kallsyms sysctl knobs as well as option to override them via a boot-time kernel parameter. Eugene Syromiatnikov (3): bpf: add ability to configure

Re: [PATCH v8 1/6] cpuset: Enable cpuset controller in default hierarchy

Hi Waiman! I've started looking at the possibility to move Android to use cgroups v2 and the availability of the cpuset controller makes this even more promising. I'll try to give a run to this series on Android, meanwhile I have some (hopefully not too much dummy) questions below. On 17-May

Re: [RFT v2 1/4] perf cs-etm: Generate sample for missed packets

Hi Leo, On 21/05/18 09:52, Leo Yan wrote: Commit e573e978fb12 ("perf cs-etm: Inject capabilitity for CoreSight traces") reworks the samples generation flow from CoreSight trace to match the correct format so Perf report tool can display the samples properly. But the change has side effect for

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

On Sat, May 05, 2018 at 12:16:13AM +0530, Ganapatrao Kulkarni wrote: > On Thu, Apr 26, 2018 at 4:29 PM, Mark Rutland wrote: > > On Wed, Apr 25, 2018 at 02:30:47PM +0530, Ganapatrao Kulkarni wrote: > >> + * > >> + * L3 Tile and DMC channel selection is through SMC call > >>

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

On Mon, May 21, 2018 at 11:37:12AM +0100, Mark Rutland wrote: > Hi Ganapat, > > > Sorry for the delay in replying; I was away most of last week. > > On Tue, May 15, 2018 at 04:03:19PM +0530, Ganapatrao Kulkarni wrote: > > On Sat, May 5, 2018 at 12:16 AM, Ganapatrao Kulkarni

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

Hi Ganapat, Sorry for the delay in replying; I was away most of last week. On Tue, May 15, 2018 at 04:03:19PM +0530, Ganapatrao Kulkarni wrote: > On Sat, May 5, 2018 at 12:16 AM, Ganapatrao Kulkarni > wrote: > > On Thu, Apr 26, 2018 at 4:29 PM, Mark Rutland

[RFT v2 1/4] perf cs-etm: Generate sample for missed packets

Commit e573e978fb12 ("perf cs-etm: Inject capabilitity for CoreSight traces") reworks the samples generation flow from CoreSight trace to match the correct format so Perf report tool can display the samples properly. But the change has side effect for packet handling, it only generate samples

[RFT v2 0/4] Perf script: Add python script for CoreSight trace disassembler

This patch series is to support for using 'perf script' for CoreSight trace disassembler, for this purpose this patch series adds a new python script to parse CoreSight tracing event and use command 'objdump' for disassembled lines, finally this can generate readable program execution flow for

[RFT v2 4/4] coresight: Document for CoreSight trace disassembler

This commit documents CoreSight trace disassembler usage and gives example for it. Signed-off-by: Leo Yan --- Documentation/trace/coresight.txt | 52 +++ 1 file changed, 52 insertions(+) diff --git a/Documentation/trace/coresight.txt

[RFT v2 2/4] perf script python: Add addr into perf sample dict

ARM CoreSight auxtrace uses 'sample->addr' to record the target address for branch instructions, so the data of 'sample->addr' is required for tracing data analysis. This commit collects data of 'sample->addr' into perf sample dict, finally can be used for python script for parsing event.