of checking that the BUSY bit is 1, works around the issue. Note
this in the customary location. To minimize conflicts, this documentation
update is separate from the code changes, "tty: pl011: Work around QDF2400
E44 stuck BUSY bit".
Signed-off-by: Christopher Covington <c...@codeauro
On 02/15/2017 03:07 PM, Greg Kroah-Hartman wrote:
> On Wed, Feb 15, 2017 at 07:50:27PM +, Mark Rutland wrote:
>> On Wed, Feb 15, 2017 at 01:01:59PM -0500, Christopher Covington wrote:
>>> Due to known (although trivial) conflicts in silicon-errata.txt, based on
>>>
and early_write functions.
Similar to what how ARMv8 ACPI PCI quirks are detected during MCFG parsing,
check the OEM fields of the Serial Port Console Redirection (SPCR) ACPI
table to determine if the current platform is known to be affected by the
erratum.
Signed-off-by: Christopher Covington &l
On 2017-02-14 21:39, Timur Tabi wrote:
Christopher Covington wrote:
The Qualcomm Datacenter Technologies QDF2400 family of SoCs contains a
custom (non-PrimeCell) implementation of the SBSA UART. Occasionally
the
BUSY bit in the Flag Register gets stuck as 1, erratum 44 for both
2432v1
On 02/08/2017 06:04 PM, Timur Tabi wrote:
> On 02/08/2017 04:22 PM, Christopher Covington wrote:
>>>> >> -while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
>>>> >> +while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
On 02/07/2017 11:05 PM, Timur Tabi wrote:
> Christopher Covington wrote:
>> The Qualcomm Datacenter Technologies QDF2400 family of SoCs contains a
>> custom (non-PrimeCell) implementation of the SBSA UART. Occasionally the
>> BUSY bit in the Flag Register gets stuck as 1
Hi,
On 02/08/2017 08:27 AM, Timur Tabi wrote:
> Robin Murphy wrote:
>> Is there a reason anyone would ever want to turn this off? AFAICS you
>> save a few dozen bytes in return for a kernel image which you know won't
>> work properly on some hardware. That doesn't seem particularly
>> worthwhile,
ora.org>
Signed-off-by: Christopher Covington <c...@codeaurora.org>
---
Documentation/arm64/silicon-errata.txt | 1 +
arch/arm64/Kconfig | 18 ++
arch/arm64/include/asm/assembler.h | 23 +++
arch/arm64/include/asm/cpucaps.h
is
available, the implementation is different than in the preceding patch.
Signed-off-by: Christopher Covington <c...@codeaurora.org>
---
drivers/tty/serial/amba-pl011.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/amba-pl0
is available, and does not handle the erratum for earlycon, as the UAP
data is not available then.
Signed-off-by: Christopher Covington <c...@codeaurora.org>
Acked-by: Russell King <rmk+ker...@armlinux.org.uk>
---
Changes between the previous RFC [1] and this PATCH:
* don't use arch/
On 02/01/2017 01:38 PM, Catalin Marinas wrote:
> On Wed, Feb 01, 2017 at 06:34:01PM +, Will Deacon wrote:
>> On Wed, Feb 01, 2017 at 06:22:44PM +, Catalin Marinas wrote:
>>> On Wed, Feb 01, 2017 at 05:59:48PM +, Will Deacon wrote:
On Wed, Feb 01, 2017 at 05:49:34PM +, Catalin
ora.org>
Signed-off-by: Christopher Covington <c...@codeaurora.org>
---
Based on
https://git.kernel.org/cgit/linux/kernel/git/arm64/linux.git/log/?h=for-next/core
---
Documentation/arm64/silicon-errata.txt | 1 +
arch/arm64/Kconfig | 12
arch/a
On 01/31/2017 12:56 PM, Marc Zyngier wrote:
> On 31/01/17 17:48, Christopher Covington wrote:
>> On 01/31/2017 07:37 AM, Mark Rutland wrote:
>>> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote:
>>>> The Qualcomm Datacenter Technologies Falkor v
On 01/31/2017 07:37 AM, Mark Rutland wrote:
> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote:
>> The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries
>> using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum
>&g
On 01/31/2017 09:38 AM, Will Deacon wrote:
> On Mon, Jan 30, 2017 at 06:08:17PM -0500, Christopher Covington wrote:
>> diff --git a/arch/arm64/include/asm/tlbflush.h
>> b/arch/arm64/include/asm/tlbflush.h
>> index deab52374119..fc434f421c7b 100644
>> --- a/arch/a
. Checking that the Transmit FIFO Empty (TXFE) bit is 0,
instead of checking that the BUSY bit is 1, works around the issue. To
facilitate this substitution, introduce vendor-specific inversion of
Feature Register bits.
Signed-off-by: Christopher Covington <c...@codeaurora.org>
---
Based on
), this changes applies the workaround overabundantly--
to local TLBI, DSB NSH sequences as well--for simplicity.
Based on work by Shanker Donthineni <shank...@codeaurora.org>
Signed-off-by: Christopher Covington <c...@codeaurora.org>
---
Based on
https://git.kernel.org/cgit/linux/kern
ora.org>
Signed-off-by: Christopher Covington <c...@codeaurora.org>
---
Based on
https://git.kernel.org/cgit/linux/kernel/git/arm64/linux.git/log/?h=for-next/core
---
Documentation/arm64/silicon-errata.txt | 1 +
arch/arm64/Kconfig | 11 +++
arch/arm64/include
Hi Mark,
On 01/30/2017 05:56 AM, Mark Rutland wrote:
> Hi,
>
> On Fri, Jan 27, 2017 at 04:52:23PM -0500, Christopher Covington wrote:
>> On 01/27/2017 09:38 AM, Mark Rutland wrote:
>>> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote:
>
>&g
Hi Mark,
On 01/27/2017 09:38 AM, Mark Rutland wrote:
> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote:
>> The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries
>> using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum
), this changes applies the workaround overabundantly--
to local TLBI, DSB NSH sequences as well--for simplicity.
Based on work by Shanker Donthineni <shank...@codeaurora.org>
Signed-off-by: Christopher Covington <c...@codeaurora.org>
---
Documentation/arm64/silicon-errata.txt | 1 +
Hi Catalin,
On 01/11/2017 01:06 PM, Catalin Marinas wrote:
> Some minor comments below, nothing fundamental (as long as you say the
> new sequence doesn't have the speculative TLB load problem I mentioned
> on a previous version).
This workaround is documented as providing functional correctness
On 01/12/2017 11:12 AM, Mark Rutland wrote:
> On Thu, Jan 12, 2017 at 03:45:48PM +, Catalin Marinas wrote:
>> On Wed, Jan 11, 2017 at 06:40:52PM +, Mark Rutland wrote:
>
>>> Likewise, I beleive we may need to modify cpu_set_reserved_ttbr0().
>>
>> This may be fine if my assumptions about
Hi Mark,
On 01/11/2017 01:45 PM, Mark Rutland wrote:
> On Wed, Jan 11, 2017 at 12:40:42PM -0600, Timur Tabi wrote:
>> On 01/11/2017 12:37 PM, Mark Rutland wrote:
>>> The name, as it is, is perfectly descriptive.
>>>
>>> Let's not sacrifice legibility over a non-issue.
>>
>> I don't want to kick a
During a TLB invalidate sequence targeting the inner shareable
domain, Falkor may prematurely complete the DSB before all loads
and stores using the old translation are observed; instruction
fetches are not subject to the conditions of this erratum.
Signed-off-by: Christopher Covington &l
amp;0 ASID is not subject to this erratum
because hardware is prohibited from performing translations from an
out-of-context translation regime.
Signed-off-by: Shanker Donthineni <shank...@codeaurora.org>
Signed-off-by: Christopher Covington <c...@codeaurora.org>
---
Documentation/arm64/s
On 01/03/2017 10:55 AM, Mark Rutland wrote:
> Hi,
>
> On Thu, Dec 29, 2016 at 05:43:32PM -0500, Christopher Covington wrote:
>> +config QCOM_FALKOR_E1003_RESERVED_ASID
>> +int
>> +default 1
>> +depends on QCOM_FALKOR_ERRATUM_1003
>> +
>
>
On 12/29/2016 06:08 PM, Timur Tabi wrote:
> On 12/29/2016 04:43 PM, Christopher Covington wrote:
>> +config QCOM_FALKOR_E1003_RESERVED_ASID
>> +int
>> +default 1
>> +depends on QCOM_FALKOR_ERRATUM_1003
>
> Also, since this can't be changed via the m
On 12/29/2016 06:02 PM, Timur Tabi wrote:
> On 12/29/2016 04:43 PM, Christopher Covington wrote:
>> -| Implementor| Component | Erratum ID | Kconfig
>>|
>> -++-+-+---
<shank...@codeaurora.org>
Signed-off-by: Christopher Covington <c...@codeaurora.org>
---
Documentation/arm64/silicon-errata.txt | 43 +-
arch/arm64/Kconfig | 16 +
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/k
During a TLB invalidate sequence targeting the inner shareable
domain, Falkor may prematurely complete the DSB before all loads
and stores using the old translation are observed; instruction
fetches are not subject to the conditions of this erratum.
Signed-off-by: Christopher Covington &l
to prctl(PR_SET_MM) or a flag
to clone. There is no prctl(PR_GET_MM). Instead such information is
expected to come from /proc//stat[m]. For the same extendability
reason, use a per-pid proc entry rather than a system-wide entry like
/proc/sys/vm/mmap_min_addr.
Signed-off-by: Christopher Covington &l
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