Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

On Sat, May 05, 2018 at 12:16:13AM +0530, Ganapatrao Kulkarni wrote: > On Thu, Apr 26, 2018 at 4:29 PM, Mark Rutland <mark.rutl...@arm.com> wrote: > > On Wed, Apr 25, 2018 at 02:30:47PM +0530, Ganapatrao Kulkarni wrote: > >> + * > >> + * L3 Tile and DMC chan

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

On Mon, May 21, 2018 at 11:37:12AM +0100, Mark Rutland wrote: > Hi Ganapat, > > > Sorry for the delay in replying; I was away most of last week. > > On Tue, May 15, 2018 at 04:03:19PM +0530, Ganapatrao Kulkarni wrote: > > On Sat, May 5, 2018 at 12:16 AM, Ganapatrao Kulk

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

Hi Ganapat, Sorry for the delay in replying; I was away most of last week. On Tue, May 15, 2018 at 04:03:19PM +0530, Ganapatrao Kulkarni wrote: > On Sat, May 5, 2018 at 12:16 AM, Ganapatrao Kulkarni <gklkm...@gmail.com> > wrote: > > On Thu, Apr 26, 2018 at 4:29 PM, Mark

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

Hi Kim, On Thu, Apr 26, 2018 at 05:06:24PM -0500, Kim Phillips wrote: > On Wed, 25 Apr 2018 14:30:47 +0530 > Ganapatrao Kulkarni wrote: > > > +static int thunderx2_uncore_event_init(struct perf_event *event) > This PMU driver can be made more user-friendly by

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

Hi, On Wed, Apr 25, 2018 at 02:30:47PM +0530, Ganapatrao Kulkarni wrote: > + > +/* L3c and DMC has 16 and 8 channels per socket respectively. > + * Each Channel supports UNCORE PMU device and consists of > + * 4 independent programmable counters. Counters are 32 bit > + * and does not support

Re: [PATCH v6 0/6] Add HiSilicon SoC uncore Performance Monitoring Unit driver

On Thu, Oct 19, 2017 at 04:28:35PM +0100, Will Deacon wrote: > On Thu, Oct 19, 2017 at 01:29:18PM +0100, Mark Rutland wrote: > > Will, are you happy to queue this? > > > > There's a minor fixup [1] needed in patch 2, but otherwise this looks > > good to me, and bu

Re: [PATCH v6 0/6] Add HiSilicon SoC uncore Performance Monitoring Unit driver

Will, are you happy to queue this? There's a minor fixup [1] needed in patch 2, but otherwise this looks good to me, and builds cleanly. I've pushed out a branch [2] with that fix folded in, in case that's easier for you. Otherwise, feel free to pick these up with my Ack. Thanks, Mark. [1]

Re: [PATCH v6 2/6] perf: hisi: Add support for HiSilicon SoC uncore PMU driver

On Thu, Oct 19, 2017 at 07:05:17PM +0800, Shaokun Zhang wrote: > This patch adds support HiSilicon SoC uncore PMU driver framework and > interfaces. > +static bool hisi_validate_event_group(struct perf_event *event) > +{ > + struct perf_event *sibling, *leader = event->group_leader; > +

Re: [PATCH v5 3/6] perf: hisi: Add support for HiSilicon SoC L3C PMU driver

On Wed, Oct 18, 2017 at 09:33:30PM +0800, Zhangshaokun wrote: > On 2017/10/17 23:16, Mark Rutland wrote: > > On Tue, Aug 22, 2017 at 04:07:54PM +0800, Shaokun Zhang wrote: > >> +static int hisi_l3c_pmu_init_data(struct platform_device *pdev, > >> +

Re: [PATCH v5 5/6] perf: hisi: Add support for HiSilicon SoC DDRC PMU driver

On Tue, Aug 22, 2017 at 04:07:56PM +0800, Shaokun Zhang wrote: > This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each > DDRC has own control, counter and interrupt registers and is an separate > PMU. For each DDRC PMU, it has 8-fixed-purpose counters which have been > mapped to

Re: [PATCH v5 4/6] perf: hisi: Add support for HiSilicon SoC HHA PMU driver

On Tue, Aug 22, 2017 at 04:07:55PM +0800, Shaokun Zhang wrote: > L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon > SoC. This patch adds support for HHA PMU driver, Each HHA has own > control, counter and interrupt registers and is an separate PMU. For > each HHA PMU, it has

Re: [PATCH v5 3/6] perf: hisi: Add support for HiSilicon SoC L3C PMU driver

On Tue, Aug 22, 2017 at 04:07:54PM +0800, Shaokun Zhang wrote: > +static int hisi_l3c_pmu_init_irq(struct hisi_pmu *l3c_pmu, > + struct platform_device *pdev) > +{ > + int irq, ret; > + > + /* Read and init IRQ */ > + irq = platform_get_irq(pdev, 0); > +

Re: [PATCH v5 2/6] perf: hisi: Add support for HiSilicon SoC uncore PMU driver

Hi, Apologies for the delay for this review. Largely this seems to look OK, but there are a couple of things which stick out. On Tue, Aug 22, 2017 at 04:07:53PM +0800, Shaokun Zhang wrote: > +int hisi_uncore_pmu_event_init(struct perf_event *event) > +{ > + struct hw_perf_event *hwc = >hw;

Re: [PATCH v4 5/6] perf: hisi: Add support for HiSilicon SoC DDRC PMU driver

On Tue, Jul 25, 2017 at 08:10:41PM +0800, Shaokun Zhang wrote: > This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each > DDRC has own control, counter and interrupt registers and is an separate > PMU. For each DDRC PMU, it has 8-fixed-purpose counters which have been > mapped to

Re: [PATCH v4 4/6] perf: hisi: Add support for HiSilicon SoC HHA PMU driver

On Tue, Jul 25, 2017 at 08:10:40PM +0800, Shaokun Zhang wrote: > +/* HHA register definition */ > +#define HHA_INT_MASK 0x0804 > +#define HHA_INT_STATUS 0x0808 > +#define HHA_INT_CLEAR0x080C > +#define HHA_PERF_CTRL0x1E00 > +#define

Re: [PATCH v4 3/6] perf: hisi: Add support for HiSilicon SoC L3C PMU driver

On Tue, Jul 25, 2017 at 08:10:39PM +0800, Shaokun Zhang wrote: > This patch adds support for L3C PMU driver in HiSilicon SoC chip, Each > L3C has own control, counter and interrupt registers and is an separate > PMU. For each L3C PMU, it has 8-programable counters and supports 0x60 > events, event

Re: [PATCH v4 2/6] perf: hisi: Add support for HiSilicon SoC uncore PMU driver

Hi, On Tue, Jul 25, 2017 at 08:10:38PM +0800, Shaokun Zhang wrote: > +/* Read Super CPU cluster and CPU cluster ID from MPIDR_EL1 */ > +void hisi_read_sccl_and_ccl_id(u32 *sccl_id, u32 *ccl_id) > +{ > + u64 mpidr; > + > + mpidr = read_cpuid_mpidr(); > + if (mpidr & MPIDR_MT_BITMASK) {

Re: [PATCH v4 1/6] Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver

Hi, On Tue, Jul 25, 2017 at 08:10:37PM +0800, Shaokun Zhang wrote: > This patch adds documentation for the uncore PMUs on HiSilicon SoC. > > Reviewed-by: Jonathan Cameron > Signed-off-by: Shaokun Zhang > Signed-off-by: Anurup M

Re: [PATCH v3 3/3] perf: xgene: Add support for SoC PMU version 3

On Thu, Jun 22, 2017 at 06:52:56PM +0100, Mark Rutland wrote: > Hi Hoan, > > This largely looks good; I have one minor comment. > > On Tue, Jun 06, 2017 at 11:02:26AM -0700, Hoan Tran wrote: > > static inline void > > +xgene_pmu_write_counter64(struct xgene_pmu_dev

Re: [PATCH v3 3/3] perf: xgene: Add support for SoC PMU version 3

On Thu, Jun 22, 2017 at 11:13:08AM -0700, Hoan Tran wrote: > On Thu, Jun 22, 2017 at 10:52 AM, Mark Rutland <mark.rutl...@arm.com> wrote: > > On Tue, Jun 06, 2017 at 11:02:26AM -0700, Hoan Tran wrote: > > > static inline void > > > +xgene_pmu_write_counter64(struc

Re: [PATCH v3 2/3] perf: xgene: Move PMU leaf functions into function pointer structure

int idx) > { > - return readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx)); > + return (u64)readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx)); > } Nit: the cast is redundant, and can go. Otherwise: Acked-by: Mark Rutland <mark.r

Re: [PATCH v3 3/3] perf: xgene: Add support for SoC PMU version 3

>start_counters() just before releasing it. With that: Acked-by: Mark Rutland <mark.rutl...@arm.com> Thanks, Mark. -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html

Re: [PATCH v3 1/3] perf: xgene: Parse PMU subnode from the match table

_id *match_id = NULL; > + const struct acpi_device_id *id; > + Since this was the subject of confusion before, can we please add a comment here, e.g. /* * We have to iterate over the list as acpi_match_device_ids() * doesn't tell us *which* entry matches, and

Re: [PATCH v2 1/3] perf: xgene: Parse PMU subnode from the match table

On Fri, Jun 02, 2017 at 09:54:32AM -0700, Hoan Tran wrote: > On Fri, Jun 2, 2017 at 7:59 AM, Mark Rutland <mark.rutl...@arm.com> wrote: > > On Mon, Apr 03, 2017 at 09:47:55AM -0700, Hoan Tran wrote: > >> +static const struct acpi_device_id *x

Re: [PATCH v2 1/3] perf: xgene: Parse PMU subnode from the match table

gene_pmu_acpi_type_match, adev); > + if (!acpi_id) > + return AE_OK; As above, and as I covered in my reply to v1, I think the above should be: acpi_id = acpi_match_device_ids(adev, xgene_pmu_acpi_type_match); if (!acpi_id) return AE_OK; ... or am I missing so

Re: [PATCH 2/2] perf: xgene: Add support for SoC PMU of next generation of X-Gene

On Tue, Mar 14, 2017 at 11:06:52AM -0700, Hoan Tran wrote: > This patch adds support for SoC-wide (AKA uncore) Performance Monitoring > Unit in the next generation of X-Gene SoC. > > Signed-off-by: Hoan Tran > --- > drivers/perf/xgene_pmu.c | 645 >

Re: [PATCH 1/2] Documentation: perf: xgene: Add support for SoC PMU of next generation of X-Gene

On Tue, Mar 14, 2017 at 11:06:51AM -0700, Hoan Tran wrote: > This patch adds support for SoC-wide (AKA uncore) Performance Monitoring > Unit in the next generation of X-Gene SoC. It adds a description, certainly. > > Signed-off-by: Hoan Tran > --- >

Re: [PATCHv3 2/2] arch: Rename CONFIG_DEBUG_RODATA and CONFIG_DEBUG_MODULE_RONX

On Thu, Feb 16, 2017 at 05:08:20PM -0800, Kees Cook wrote: > On Thu, Feb 16, 2017 at 2:25 PM, Pavel Machek wrote: > > Hi! > > > >> > >> -config DEBUG_RODATA > >> +config STRICT_KERNEL_RWX > >> bool "Make kernel text and rodata read-only" if > >> ARCH_OPTIONAL_KERNEL_RWX > >>

Re: [PATCH v3] tty: pl011: Work around QDF2400 E44 stuck BUSY bit

EM_TABLE_ID_SIZE) && > + h->oem_revision == 0) > + return true; > + > + return false; > +} > + > /** > * parse_spcr() - parse ACPI SPCR table and add preferred console > * > @@ -93,6 +113,9 @@ int __init parse_sp

Re: [PATCH v2] tty: pl011: Work around QDF2400 E44 stuck BUSY bit

if (!memcmp(id, "QDF2000 ", ACPI_OEM_TABLE_ID_SIZE) && > h->oem_revision == 0) > return True; > > return False; > } s/False/false/g s/True/true/g With that, this looks fine to me. I'm not too familiar with the pl011

Re: [PATCH 1/2] tty: pl011: Work around QDF2400 E44 stuck BUSY bit

On Wed, Feb 08, 2017 at 07:27:29AM -0600, Timur Tabi wrote: > Robin Murphy wrote: > >Are we to take it that every SoC now and always with any Kryo or Falkor > >core which also has an SBSA UART will require this workaround? > > No, only Kryo and Falkor V1 based SOCs have this problem. Falkor V2

Re: [PATCHv2 2/2] arch: Rename CONFIG_DEBUG_RODATA and CONFIG_DEBUG_MODULE_RONX

> options do. > > Signed-off-by: Laura Abbott <labb...@redhat.com> As with patch 1, this looks good to me. FWIW: Acked-by: Mark Rutland <mark.rutl...@arm.com> > diff --git a/arch/arm64/Kconfig.debug b/arch/arm64/Kconfig.debug > index 939815e..560a8d8 100644 > --- a/a

Re: [PATCHv2 1/2] arch: Move CONFIG_DEBUG_RODATA and CONFIG_SET_MODULE_RONX to be common

ion and make these options def_bool y for almost all of those > arches. > > Signed-off-by: Laura Abbott <labb...@redhat.com> >From my POV this looks good. FWIW: Acked-by: Mark Rutland <mark.rutl...@arm.com> Mark. > --- > v2: This patch is now doing just the refactor of

Re: [PATCH v5 2/2] arm64: Work around Falkor erratum 1009

ra.org> > > Signed-off-by: Christopher Covington <c...@codeaurora.org> This looks simple, self-contained, and correct, so FWIW: Acked-by: Mark Rutland <mark.rutl...@arm.com> Catalin/Will, since we may see a documentation conflict against a timer erratum, would you be hapyp

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: > The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries > using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum > is triggered, page table entries using the new translation table base >

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: > The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries > using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum > is triggered, page table entries using the new translation table base >

Re: [PATCH 2/2] security: Change name of CONFIG_DEBUG_SET_MODULE_RONX

Hi, On Wed, Jan 18, 2017 at 05:29:06PM -0800, Laura Abbott wrote: > > Despite the word 'debug' in CONFIG_DEBUG_SET_MODULE_RONX, this kernel > option provides key security features that are to be expected on a > modern system. Change the name to CONFIG_HARDENED_MODULE_MAPPINGS which > more

Re: [PATCH 1/2] security: Change name of CONFIG_DEBUG_RODATA

Hi Laura, On Wed, Jan 18, 2017 at 05:29:05PM -0800, Laura Abbott wrote: > > Despite the word 'debug' in CONFIG_DEBUG_RODATA, this kernel option > provides key security features that are to be expected on a modern > system. Change the name to CONFIG_HARDENED_PAGE_MAPPINGS which more > accurately

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

On Wed, Jan 11, 2017 at 12:40:42PM -0600, Timur Tabi wrote: > On 01/11/2017 12:37 PM, Mark Rutland wrote: > >The name, as it is, is perfectly descriptive. > > > >Let's not sacrifice legibility over a non-issue. > > I don't want to kick a dead hors

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

On Wed, Jan 11, 2017 at 06:22:08PM +, Marc Zyngier wrote: > On 11/01/17 18:06, Catalin Marinas wrote: > > On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote: > >> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S > >> index 32682be..9ee46df 100644 > >> ---

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

On Wed, Jan 11, 2017 at 12:35:55PM -0600, Timur Tabi wrote: > On 01/11/2017 12:33 PM, Mark Rutland wrote: > >It'll need to affect all lines since the kconfig column needs to expand > >by at least one character to fit QCOM_FALKOR_ERRATUM_1003. > > Or we can make the mac

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

On Wed, Jan 11, 2017 at 06:06:27PM +, Catalin Marinas wrote: > On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote: > > -| Implementor| Component | Erratum ID | Kconfig > > | > > +| Implementor | Component | Erratum ID | Kconfig

Re: [PATCH v3 04/10] Documentation: perf: hisi: Documentation for HiP05/06/07 PMU event counting.

On Mon, Jan 02, 2017 at 01:49:37AM -0500, Anurup M wrote: > +The Hisilicon SoC HiP05/06/07 chips consist of various independent system > +device PMU's such as L3 cache(L3C) and Miscellaneous Nodes(MN). > +These PMU devices are independent and have hardware logic to gather > +statistics and

[PATCH] Documentation: atomic_ops: use {READ,WRITE}_ONCE()

() macros as appropriate. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: Boqun Feng <boqun.f...@gmail.com> Cc: Jonathan Corbet <cor...@lwn.net> Cc: Paul E. McKenney <paul...@linux.vnet.ibm.com> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Will Deacon <w

[PATCH] Documentation: circular-buffers: use READ_ONCE()

(), as ACCESS_ONCE() is only used in a reader context in the circular buffer documentation. Signed-off-by: Mark Rutland <mark.rutl...@arm.com> Cc: David Howells <dhowe...@redhat.com> Cc: Jonathan Corbet <cor...@lwn.net> Cc: Paul E. McKenney <paul...@linux.vnet.ibm.com> Cc: linu

Re: [RESEND PATCH v1 05/11] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU

On Mon, Nov 14, 2016 at 05:36:44AM +0530, Anurup M wrote: > On Friday 11 November 2016 12:00 AM, Mark Rutland wrote: > >On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote: > >>+ - scl-id : The Super Cluster ID. This can be the ID of the CPU die > >>+

Re: [RESEND PATCH v1 02/11] dt-bindings: hisi: Add Hisilicon HiP05/06/07 Sysctrl and Djtag dts bindings

On Fri, Nov 11, 2016 at 04:49:03PM +0530, Anurup M wrote: > On Thursday 10 November 2016 10:53 PM, Mark Rutland wrote: > >On Thu, Nov 03, 2016 at 01:41:58AM -0400, Anurup M wrote: > >>diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt > >>

Re: [RESEND PATCH v1 07/11] perf: hisi: Add support for Hisilicon SoC event counters

On Thu, Nov 03, 2016 at 01:42:03AM -0400, Anurup M wrote: > + do { > + /* Get count from individual L3C banks and sum them up */ > + for (i = 0; i < num_banks; i++) { > + total_raw_count += hisi_read_l3c_counter(l3c_hwmod_data, > +

Re: [RESEND PATCH v1 05/11] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU

Hi, On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote: > 1) Device tree bindings for Hisilicon SoC PMU. > 2) Add example for Hisilicon L3 cache, MN and DDRC PMU. > > Signed-off-by: Anurup M > Signed-off-by: Shaokun Zhang > ---

Re: [RESEND PATCH v1 03/11] drivers: soc: hisi: Add support for Hisilicon Djtag driver

On Thu, Nov 03, 2016 at 01:41:59AM -0400, Anurup M wrote: > From: Tan Xiaojun > > The Hisilicon Djtag is an independent component which connects > with some other components in the SoC by Debug Bus. This driver > can be configured to access the registers

Re: [RESEND PATCH v1 02/11] dt-bindings: hisi: Add Hisilicon HiP05/06/07 Sysctrl and Djtag dts bindings

Hi, On Thu, Nov 03, 2016 at 01:41:58AM -0400, Anurup M wrote: > From: Tan Xiaojun > > 1) Add Hisilicon HiP05/06/07 CPU and ALGSUB system controller dts > bindings. > 2) Add Hisilicon Djtag dts binding. > > Signed-off-by: Tan Xiaojun

Re: [kernel-hardening] [PATCH 1/2] security, perf: allow further restriction of perf_event_open

On Mon, Oct 17, 2016 at 10:54:33AM -0400, Daniel Micay wrote: > On Mon, 2016-10-17 at 14:44 +0100, Mark Rutland wrote: > > It's also my understanding that for Android, perf_event_paranoid is > > lowered when the user enables developer mode (rather than only when an > &

Re: [kernel-hardening] [PATCH 1/2] security, perf: allow further restriction of perf_event_open

On Tue, Oct 18, 2016 at 05:15:01PM -0400, Daniel Micay wrote: > It's also worth noting that fine-grained control via a scoped > mechanism would likely only be used to implement *more restrictions* > on Android, not to make the feature less aggressive. It's desirable > for perf events to be

Re: [kernel-hardening] [PATCH 1/2] security, perf: allow further restriction of perf_event_open

Hi, Attempt to revive discussions below... On Wed, Jul 27, 2016 at 07:45:46AM -0700, Jeff Vander Stoep wrote: > When kernel.perf_event_paranoid is set to 3 (or greater), disallow > all access to performance events by users without CAP_SYS_ADMIN. > > This new level of restriction is intended to

Re: [kernel-hardening] Re: [PATCH 1/2] security, perf: allow further restriction of perf_event_open

On Thu, Aug 04, 2016 at 12:32:32PM -0400, Daniel Micay wrote: > On Thu, 2016-08-04 at 17:10 +0100, Mark Rutland wrote: > I wasn't talking specifically about perf. Then this is irrelevant to a discussion about limiting access to the perf interface. Hardening drivers in general is

Re: [kernel-hardening] Re: [PATCH 1/2] security, perf: allow further restriction of perf_event_open

On Thu, Aug 04, 2016 at 11:44:28AM -0400, Daniel Micay wrote: > Qualcomm's drivers might be lower quality than core kernel code, but > they're way above the baseline set by mainline kernel drivers... I don't think that's true for the arm/arm64 perf code. I think we've done a reasonable job of

Re: [kernel-hardening] Re: [PATCH 1/2] security, perf: allow further restriction of perf_event_open

On Wed, Aug 03, 2016 at 03:36:16PM -0400, Daniel Micay wrote: > There's a lot of architecture and vendor specific perf events code and > lots of bleeding edge features. On Android, a lot of the perf events > vulnerabilities have been specific to the Qualcomm SoC platform. Other > platforms are

Re: [PATCH 7/8] uio: bind uio_dmem_genirq via OF

On Fri, Jul 15, 2016 at 09:57:28PM +0530, Anup Patel wrote: > On Fri, Jul 15, 2016 at 6:58 PM, Mark Rutland <mark.rutl...@arm.com> wrote: > > On Fri, Jul 15, 2016 at 02:34:02PM +0530, Anup Patel wrote: > >> +static char uio_of_dma_bits_prop[128] = "uio

Re: [PATCH 7/8] uio: bind uio_dmem_genirq via OF

[adding devicetree list] On Fri, Jul 15, 2016 at 02:34:02PM +0530, Anup Patel wrote: > From: Jan Viktorin > > The uio_dmem_genirq works in a similar ways as uio_pdrv_genirq now. > > It accepts the of_id module parameter to specify UIO compatible > string as module

Re: [PATCH v3 2/7] leds: documentation: 'ide-disk' to 'disk-activity'

On Wed, Jun 22, 2016 at 09:55:43AM +0200, Jacek Anaszewski wrote: > On 06/21/2016 05:05 PM, Mark Rutland wrote: > >On Thu, Jun 09, 2016 at 12:29:37AM +0200, Stephan Linz wrote: > >>Cc: Joseph Jezak <jos...@gentoo.org> > >>Cc: Nico Macrionitis <ac...@

Re: [PATCH v3 2/7] leds: documentation: 'ide-disk' to 'disk-activity'

On Thu, Jun 09, 2016 at 12:29:37AM +0200, Stephan Linz wrote: > Cc: Joseph Jezak > Cc: Nico Macrionitis > Cc: Jörg Sommer > Signed-off-by: Stephan Linz > --- > Documentation/devicetree/bindings/leds/common.txt| 2