Re: [PATCH v5 0/2] perf: riscv: Preliminary Perf Event Support on RISC-V

On Tue, 24 Apr 2018 20:19:36 PDT (-0700), alan...@andestech.com wrote: Hi Atish, Palmer, On Tue, Apr 24, 2018 at 06:15:49PM -0700, Atish Patra wrote: On 4/24/18 5:29 PM, Palmer Dabbelt wrote: >On Tue, 24 Apr 2018 15:16:16 PDT (-0700), atish.pa...@wdc.com wrote: >>On 4/24/18 12:44 P

Re: [PATCH v5 0/2] perf: riscv: Preliminary Perf Event Support on RISC-V

On Tue, 24 Apr 2018 18:15:49 PDT (-0700), atish.pa...@wdc.com wrote: On 4/24/18 5:29 PM, Palmer Dabbelt wrote: On Tue, 24 Apr 2018 15:16:16 PDT (-0700), atish.pa...@wdc.com wrote: On 4/24/18 12:44 PM, Palmer Dabbelt wrote: On Tue, 24 Apr 2018 12:27:26 PDT (-0700), atish.pa...@wdc.com wrote

Re: [PATCH v5 0/2] perf: riscv: Preliminary Perf Event Support on RISC-V

On Tue, 24 Apr 2018 15:16:16 PDT (-0700), atish.pa...@wdc.com wrote: On 4/24/18 12:44 PM, Palmer Dabbelt wrote: On Tue, 24 Apr 2018 12:27:26 PDT (-0700), atish.pa...@wdc.com wrote: On 4/24/18 11:07 AM, Atish Patra wrote: On 4/19/18 4:28 PM, Alan Kao wrote: However, I got an rcu-stall

Re: [PATCH v5 0/2] perf: riscv: Preliminary Perf Event Support on RISC-V

On Tue, 24 Apr 2018 12:27:26 PDT (-0700), atish.pa...@wdc.com wrote: On 4/24/18 11:07 AM, Atish Patra wrote: On 4/19/18 4:28 PM, Alan Kao wrote: This implements the baseline PMU for RISC-V platforms. To ease future PMU portings, a guide is also written, containing perf concepts, arch porting

Re: [PATCH v2 1/2] mm: introduce ARCH_HAS_PTE_SPECIAL

On Tue, 10 Apr 2018 09:09:32 PDT (-0700), wi...@infradead.org wrote: On Tue, Apr 10, 2018 at 05:25:50PM +0200, Laurent Dufour wrote: arch/powerpc/include/asm/pte-common.h | 3 --- arch/riscv/Kconfig | 1 + arch/s390/Kconfig

Re: [PATCH 1/2] perf: riscv: preliminary RISC-V support

On Mon, 09 Apr 2018 00:07:11 PDT (-0700), alan...@andestech.com wrote: On Thu, Apr 05, 2018 at 09:47:50AM -0700, Palmer Dabbelt wrote: On Mon, 26 Mar 2018 00:57:54 PDT (-0700), alan...@andestech.com wrote: >This patch provide a basic PMU, riscv_base_pmu, which supports two >general ha

Re: [PATCH 1/2] perf: riscv: preliminary RISC-V support

On Mon, 26 Mar 2018 00:57:54 PDT (-0700), alan...@andestech.com wrote: This patch provide a basic PMU, riscv_base_pmu, which supports two general hardware event, instructions and cycles. Furthermore, this PMU serves as a reference implementation to ease the portings in the future.

Re: [PATCH 0/2] perf: riscv: Preliminary Perf Event Support on RISC-V

On Wed, 04 Apr 2018 22:02:29 PDT (-0700), alan...@andestech.com wrote: On Tue, Apr 03, 2018 at 03:45:17PM -0700, Palmer Dabbelt wrote: On Tue, 03 Apr 2018 07:29:02 PDT (-0700), alan...@andestech.com wrote: >On Mon, Apr 02, 2018 at 08:15:44PM -0700, Palmer Dabbelt wrote: >>On Mon, 02 Ap

Re: [PATCH 0/2] perf: riscv: Preliminary Perf Event Support on RISC-V

On Mon, 02 Apr 2018 05:31:22 PDT (-0700), alan...@andestech.com wrote: This implements the baseline PMU for RISC-V platforms. To ease future PMU portings, a guide is also written, containing perf concepts, arch porting practices and some hints. Changes in v2: - Fix the bug reported by Alex,

Re: [PATCH 00/16] remove eight obsolete architectures

On Thu, 15 Mar 2018 03:42:25 PDT (-0700), Arnd Bergmann wrote: On Thu, Mar 15, 2018 at 10:59 AM, Hannes Reinecke wrote: On 03/15/2018 10:42 AM, David Howells wrote: Do we have anything left that still implements NOMMU? RISC-V ? (evil grin :-) Is anyone producing a chip that

Re: [PATCH] Documentation: atomic_ops.txt is core-api/atomic_ops.rst

On Fri, 23 Jun 2017 13:29:54 PDT (-0700), cor...@lwn.net wrote: > On Fri, 23 Jun 2017 13:25:22 -0700 > Palmer Dabbelt <pal...@dabbelt.com> wrote: > >> I was reading the memory barries documentation in order to make sure the >> RISC-V barries were correct, and I found

[PATCH] Documentation: atomic_ops.txt is core-api/atomic_ops.rst

I was reading the memory barries documentation in order to make sure the RISC-V barries were correct, and I found a broken link to the atomic operations documentation. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> Acked-by: Will Deacon <will.dea...@arm.com> --- Document

[PATCH] Documentation: atomic_ops.txt is core-api/atomic_ops.rst

I was reading the memory barries documentation in order to make sure the RISC-V barries were correct, and I found a broken link to the atomic operations documentation. Signed-off-by: Palmer Dabbelt <pal...@dabbelt.com> Acked-by: Will Deacon <will.dea...@arm.com> --- Document

Re: [PATCH 03/20] asm-generic: Drop getrlimit and setrlimit syscalls from default list

On Tue, 20 Jun 2017 08:27:36 PDT (-0700), Arnd Bergmann wrote: > On Tue, Jun 20, 2017 at 4:54 PM, Yury Norov wrote: >> On Tue, Jun 20, 2017 at 04:20:43PM +0200, Arnd Bergmann wrote: >>> On Tue, Jun 20, 2017 at 3:37 PM, Yury Norov >>> wrote: