element in a third vector.
This patch detects this feature and let the userspace know about it via a
HWCAP bit and MRS emulation.
Cc: Dave Martin <dave.mar...@arm.com>
Cc: Suzuki K Poulose <suzuki.poul...@arm.com>
Signed-off-by: Dongjiu Geng <gengdong...@huawei.com>
Review
Hi gengdongjiu
Sorry for the late response. I have a similar patch to add the support
for "FHM", which I was about to post it this week.
On 11/12/17 13:29, Dave Martin wrote:
On Mon, Dec 11, 2017 at 08:47:00PM +0800, gengdongjiu wrote:
On 2017/12/11 19:59, Dave P Martin wrote:
On Sat, Dec
On 19/05/17 18:44, Sudeep Holla wrote:
Hi Suzuki, Leo,
On 19/05/17 05:25, Leo Yan wrote:
From: Suzuki K Poulose <suzuki.poul...@arm.com>
Add Coresight CPU debug nodes for Juno r0, r1 & r2. The CPU
debug areas are mapped at the same address for all revisions,
like the ETM, even thoug
e parameter or sysfs
to constrain all or partial idle states to ensure the CPU power
domain is enabled and access coresight CPU debug component safely.
Signed-off-by: Leo Yan <leo@linaro.org>
With comments from Mathieu addressed,
Reviewed-by: Suzuki K Poulose <suzuki.poul...@arm
On 19/04/17 15:28, Leo Yan wrote:
Hi Suzuki,
On Wed, Apr 19, 2017 at 02:23:04PM +0100, Suzuki K Poulose wrote:
Hi Leo,
This version looks good to me. I have two minor comments below.
Thanks for reviewing. Will take the suggestions. Just check a bit for
last comment.
[...]
+static int
On 06/04/17 14:30, Leo Yan wrote:
Coresight includes debug module and usually the module connects with CPU
debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
description for related info in "Part H: External Debug".
Chapter H7 "The Sample-based Profiling Extension"
<mike.le...@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poir...@linaro.org>
Signed-off-by: Leo Yan <leo@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poul...@arm.com>
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To unsubscribe from this list: send the line "unsubscribe linux-doc"
n <leo@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poul...@arm.com>
- if (found)
- break;
- }
- of_node_put(dn);
-
- /* Affinity to CPU0 if no cpu nodes are found */
- pdata->cpu = found ? cpu :
On 30/03/17 02:03, Leo Yan wrote:
On Wed, Mar 29, 2017 at 03:56:23PM +0100, Mike Leach wrote:
[...]
+ /*
+* Unfortunately the CPU cannot be powered up, so return
+* back and later has no permission to access other
+* registers. For this case, should set 'idle_constraint'
+*
On 29/03/17 11:37, Leo Yan wrote:
On Wed, Mar 29, 2017 at 11:31:03AM +0100, Suzuki K Poulose wrote:
On 29/03/17 11:27, Leo Yan wrote:
On Wed, Mar 29, 2017 at 10:07:07AM +0100, Suzuki K Poulose wrote:
[...]
+ if (mode == EDDEVID_IMPL_NONE) {
+ drvdata->edpcsr_pres
On 29/03/17 11:27, Leo Yan wrote:
On Wed, Mar 29, 2017 at 10:07:07AM +0100, Suzuki K Poulose wrote:
[...]
+ if (mode == EDDEVID_IMPL_NONE) {
+ drvdata->edpcsr_present = false;
+ drvdata->edcidsr_present = false;
+ drvdata->edvids
On 29/03/17 04:07, Leo Yan wrote:
Hi Suzuki,
On Mon, Mar 27, 2017 at 05:34:57PM +0100, Suzuki K Poulose wrote:
On 25/03/17 18:23, Leo Yan wrote:
[...]
Leo,
Thanks a lot for the quick rework. I don't fully understand (yet!) why we need
the
idle_constraint. I will leave it for Sudeep
On 25/03/17 18:23, Leo Yan wrote:
Coresight includes debug module and usually the module connects with CPU
debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
description for related info in "Part H: External Debug".
Chapter H7 "The Sample-based Profiling Extension"
On 08/04/16 11:24, Marc Zyngier wrote:
On 08/04/16 10:58, Suzuki K Poulose wrote:
On 07/04/16 18:31, Marc Zyngier wrote:
+ All system register encodings above use the form
+
+ Op0, Op1, CRn, CRm, Op2.
+
+ Note that some of the encodings listed above include
On 07/04/16 18:31, Marc Zyngier wrote:
+ All system register encodings above use the form
+
+ Op0, Op1, CRn, CRm, Op2.
+
+ Note that some of the encodings listed above include
+ the system register space reserved for the following
+ identification registers which
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