在 2017-08-22 13:23，Icenowy Zheng 写道：
The compatible string for Allwinner V3s SoC used to be missing.
Add it to the binding document.
Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC")
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Maxime,
Ping. Have you check
在 2017-08-22 13:23，Icenowy Zheng 写道：
The compatible string for Allwinner V3s SoC used to be missing.
Add it to the binding document.
Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC")
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Maxime, Chen-Yu, ping.
The Allwinner V3s SoC is not quad-core, but single-core.
Fix this in the README file.
Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC")
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Documentation/arm/sunxi/README | 9 +
1 file changed, 5 insertions
Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
like A20.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v2:
- Fix alphabetical orders.
Documentation/arm/sunxi/README | 6 ++
Documentation/devicetree/bindin
The compatible string for Allwinner V3s SoC used to be missing.
Add it to the binding document.
Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC")
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
1 file chan
在 2017-08-21 17:34，Maxime Ripard 写道：
Hi,
On Sun, Aug 20, 2017 at 01:29:57PM +0800, Icenowy Zheng wrote:
Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
like A20.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Documentation/arm/sunxi/
Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
like A20.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Documentation/arm/sunxi/README | 6 ++
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
arch/arm/mach-sunxi/s
The compatible string for Allwinner V3s SoC used to be missing.
Add it to the binding document.
Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC")
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
1 file chan
在 2017-08-12 12:04，Chen-Yu Tsai 写道：
On Sat, Jul 22, 2017 at 11:00 AM, <icen...@aosc.io> wrote:
在 2017-05-29 15:34，Chen-Yu Tsai 写道：
Hi,
On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote:
[...]
+
+/*
+ * For the special bit in gate part, please see the BSP sourc
在 2017-05-29 15:34，Chen-Yu Tsai 写道：
Hi,
On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote:
Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.
Add support for it.
Signed-off-by: Icenowy Zheng <i
在 2017-05-29 21:11，Chen-Yu Tsai 写道：
On Sat, May 27, 2017 at 06:23:04PM +0800, Icenowy Zheng wrote:
R40 is said to be an upgrade of A20, and its pin configuration is also
similar to A20 (and thus similar to A10).
Add support for R40 to the A10 pinctrl driver.
Signed-off-by: Icenowy Zheng <i
00 MP2
GPU. It retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3
Allwinner R40 has a pin controller like the ones in older Allwinner SoCs
(especially A20), and can use modified version of the A10/A20 pinctrl
driver.
Add a compatible string for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in
Allwinner A10, A20 and R40 SoCs have similar GPIO layout.
Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support
into A10 driver, and add R40 support into it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Commit message change.
drivers/pinctrl/sunxi/p
Allwinner R40 has a clock controlling unit like the ones on other
Allwinner SoCs after sun6i, and can also use a CCU-based driver.
Add a compatible string for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Rob Herring <r...@kernel.org>
---
Changes in v3:
- Rebased on c
power, reset, and boot control buttons
This patch adds a dts file that enables debug UART and MMC support.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Pinmux changes.
arch/arm/boot/dts/Makefile
As A20 is designed as a pin-compatible upgrade of A10, their pin
controller are very similar, and can share one driver.
Add A20 support to the A10 driver.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Enable A10 driver for A20 and disable A20 driver in this
Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Rebased on current linux-next.
Changes in v2:
- Fixes according to the SoC'
R40 is said to be an upgrade of A20, and its pin configuration is also
similar to A20 (and thus similar to A10).
Add support for R40 to the A10 pinctrl driver.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/pinctrl/sunxi/Kconfig | 2 +-
drivers/pinctrl/sunxi/p
As we added A20 support to A10 pinctrl driver, now we can delete the
dedicated A20 pinctrl driver, which is duplicated code.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Only remove the A20 driver(A10 driver for A20 is enabled in
the previous commit now).
d
file for Allwinner R40
ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra
Icenowy Zheng (8):
arm: sunxi: add support for R40 SoC
pinctrl: sunxi: Add SoC ID definitions for A10, A20 and R40 SoCs
pinctrl: sunxi: add A20 support to A10 driver
pinctrl: sunxi: drop dedicated A20 driver
Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
like A20.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v3:
- Use V1.0 documents.
Documentation/arm/sunxi/README | 6 ++
Documentation/devicetree/bindings/arm/sun
From: Icenowy Zheng <icen...@aosc.xyz>
Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
like A20.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
Documentation/arm/sunxi/README | 4
Documentation/devicetree/
From: Icenowy Zheng <icen...@aosc.xyz>
Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.
Add support for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Changes in v2:
- Fixes according to the SoC's
Allwinner R40 has a clock controlling unit like the ones on other
Allwinner SoCs after sun6i, and can also use a CCU-based driver.
Add a compatible string for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 1 +
1 file chan
R40 is said to be an upgrade of A20, and its pin configuration is also
similar to A20 (and thus similar to A10).
Add support for R40 to the A10 pinctrl driver.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/pinctrl/sunxi/Kconfig | 2 +-
drivers/pinctrl/sunxi/p
Allwinner R40 has a pin controller like the ones in older Allwinner SoCs
(especially A20), and can use modified version of the A10/A20 pinctrl
driver.
Add a compatible string for it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
Documentation/devicetree/bindings/pinctrl/allwinner
As we added A20 support to A10 pinctrl driver, now we can delete the
dedicated A20 pinctrl driver, and enable A10 driver for A20.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/pinctrl/sunxi/Kconfig |6 +-
drivers/pinctrl/sunxi/Makefile|1 -
d
00 MP2
GPU. It retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.
Signed-off-by: Chen-Yu Tsai <w...@csie.org>
Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
---
arch/arm/boot/
于 2017年5月4日 GMT+08:00 下午10:41:52, Maxime Ripard
<maxime.rip...@free-electrons.com> 写到:
>On Thu, May 04, 2017 at 10:03:26PM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2017年5月4日 GMT+08:00 下午10:02:20, Maxime Ripard
><maxime.rip...@free-electrons.com> 写到:
>>
As A20 is designed as a pin-compatible upgrade of A10, their pin
controller are very similar, and can share one driver.
Add A20 support to the A10 driver.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 287 +++---
Allwinner A10, A20 and R40 SoCs have similar GPIO layout.
Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support
into A10 driver, and add R40 support into it.
Signed-off-by: Icenowy Zheng <icen...@aosc.io>
---
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 3 +++
1 file chan
于 2017年5月4日 GMT+08:00 下午10:04:31, Maxime Ripard
<maxime.rip...@free-electrons.com> 写到:
>On Thu, May 04, 2017 at 09:49:58PM +0800, Icenowy Zheng wrote:
>> Allwinner A10, A20 and R40 SoCs have similar GPIO layout.
>>
>> Add SoC definitions in pinctrl-sunxi.h, in
于 2017年5月4日 GMT+08:00 下午10:02:20, Maxime Ripard
<maxime.rip...@free-electrons.com> 写到:
>On Thu, May 04, 2017 at 09:49:59PM +0800, Icenowy Zheng wrote:
>> static const struct of_device_id sun4i_a10_pinctrl_match[] = {
>> -{ .compatible = "a
file for Allwinner R40
ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra
Icenowy Zheng (8):
arm: sunxi: add support for R40 SoC
pinctrl: sunxi: add definitions for add A20 and R40 support to A10
driver
pinctrl: sunxi: add A20 support to A10 driver
pinctrl: sunxi: switch A20's
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