Re: [PATCH v2 0/7] mm: pages for hugetlb's overcommit may be able to charge to memcg

On 2018/05/25 2:45, Mike Kravetz wrote: [...] >> THP does not guarantee to use the Huge Page, but may use the normal page. > > Note. You do not want to use THP because "THP does not guarantee". [...] >> One of the answers I have reached is to use HugeTLBfs by overcommitting >> without creating

Re: [PATCH v2 0/7] mm: pages for hugetlb's overcommit may be able to charge to memcg

On 2018/05/24 22:24, Michal Hocko wrote [...]> I do not see anything like that. adjust_pool_surplus is simply and > accounting thing. At least the last time I've checked. Maybe your > patchset handles that? As you said, my patch did not consider handling when manipulating the pool. And even if

Re: [PATCH bpf-next v2 0/3] bpf: add boot parameters for sysctl knobs

On Thu, May 24, 2018 at 09:41:08AM +0200, Jesper Dangaard Brouer wrote: > On Wed, 23 May 2018 15:02:45 -0700 > Alexei Starovoitov wrote: > > > On Wed, May 23, 2018 at 02:18:19PM +0200, Eugene Syromiatnikov wrote: > > > Some BPF sysctl knobs affect the loading of BPF

[PATCH 2/3] PCI: Allow specifying devices using a base bus and path of devfns

When specifying PCI devices on the kernel command line using a BDF, the bus numbers can change when adding or replacing a device, changing motherboard firmware, or applying kernel parameters like pci=assign-buses. When this happens, it is usually undesirable to apply whatever command line tweak to

[PATCH 0/3] Add parameter for disabling ACS redirection for P2P

Hi, As discussed in our PCI P2PDMA series, we'd like to add a kernel parameter for selectively disabling ACS redirection for select bridges. Seeing this turned out to be a small series in itself, we've decided to send this separately from the P2P work. This series generalizes the code already

[PATCH 3/3] PCI: Introduce the disable_acs_redir parameter

In order to support P2P traffic on a segment of the PCI hierarchy, we must be able to disable the ACS redirect bits for select PCI bridges. The bridges must be selected before the devices are discovered by the kernel and the IOMMU groups created. Therefore, a kernel command line parameter is

[PATCH 1/3] PCI: Make specifying PCI devices in kernel parameters reusable

Separate out the code to match a PCI device with a string (typically originating from a kernel parameter) from the pci_specified_resource_alignment() function into its own helper function. While we are at it, this change fixes the kernel style of the function (fixing a number of long lines and

Re: [PATCH v8 3/6] cpuset: Add cpuset.sched.load_balance flag to v2

On 05/24/2018 11:43 AM, Peter Zijlstra wrote: > On Thu, May 17, 2018 at 04:55:42PM -0400, Waiman Long wrote: >> The sched.load_balance flag is needed to enable CPU isolation similar to >> what can be done with the "isolcpus" kernel boot parameter. Its value >> can only be changed in a scheduling

Re: [PATCH v8 2/6] cpuset: Add new v2 cpuset.sched.domain flag

On 05/24/2018 11:41 AM, Peter Zijlstra wrote: > On Thu, May 17, 2018 at 04:55:41PM -0400, Waiman Long wrote: >> A new cpuset.sched.domain boolean flag is added to cpuset v2. This new >> flag indicates that the CPUs in the current cpuset should be treated >> as a separate scheduling domain. > The

Re: [PATCHv5 2/8] arm64: dts: stratix10: add stratix10 service driver binding to base dtsi

Hi Richard, On Thu, May 24, 2018 at 11:33:14AM -0500, richard.g...@linux.intel.com wrote: > From: Richard Gong > > Add Intel Stratix10 service layer to the device tree > > Signed-off-by: Richard Gong > Signed-off-by: Alan Tull

Re: [PATCHv5 1/8] dt-bindings, firmware: add Intel Stratix10 service layer binding

On Thu, May 24, 2018 at 11:33:13AM -0500, richard.g...@linux.intel.com wrote: > From: Richard Gong > > Add a device tree binding for the Intel Stratix10 service layer driver > > Signed-off-by: Richard Gong > Signed-off-by: Alan Tull

[PATCHv5 4/8] dt-bindings: fpga: add Stratix10 SoC FPGA manager binding

From: Alan Tull Add a Device Tree binding for the Intel Stratix10 SoC FPGA manager. Signed-off-by: Alan Tull Signed-off-by: Richard Gong Reviewed-by: Rob Herring --- v2: this patch is added in patch set version 2

[PATCHv5 2/8] arm64: dts: stratix10: add stratix10 service driver binding to base dtsi

From: Richard Gong Add Intel Stratix10 service layer to the device tree Signed-off-by: Richard Gong Signed-off-by: Alan Tull --- v2: Change to put service layer driver node under the firmware node Change compatible to

[PATCHv5 1/8] dt-bindings, firmware: add Intel Stratix10 service layer binding

From: Richard Gong Add a device tree binding for the Intel Stratix10 service layer driver Signed-off-by: Richard Gong Signed-off-by: Alan Tull Reviewed-by: Rob Herring --- v2: Change to put service layer

[PATCHv5 7/8] defconfig: enable fpga and service layer

From: Richard Gong Enable fpga framework, Stratix 10 SoC FPGA manager and Stratix10 Service Layer Signed-off-by: Richard Gong Signed-off-by: Alan Tull --- v2: this patch is added in patch set version 2 v3: no change v4:

[PATCHv5 3/8] driver, misc: add Intel Stratix10 service layer driver

From: Richard Gong Some features of the Intel Stratix10 SoC require a level of privilege higher than the kernel is granted. Such secure features include FPGA programming. In terms of the ARMv8 architecture, the kernel runs at Exception Level 1 (EL1), access to the

[PATCHv5 6/8] fpga: add intel stratix10 soc fpga manager driver

From: Alan Tull Add driver for reconfiguring Intel Stratix10 SoC FPGA devices. This driver communicates through the Intel Service Driver which does communication with privileged hardware (that does the FPGA programming) through a secure mailbox. Signed-off-by: Alan Tull

[PATCHv5 8/8] Documentation: driver-api: add stratix10 service layer

From: Richard Gong Add new file stratix10-svc.rst Add stratix10-svc.rst to driver-api/index.rst Signed-off-by: Richard Gong Signed-off-by: Alan Tull --- v5: this patch is added in patch set version 5 ---

[PATCHv5 5/8] arm64: dts: stratix10: add fpga manager and region

From: Alan Tull Add the Stratix10 FPGA manager and a FPGA region to the device tree. Signed-off-by: Alan Tull Signed-off-by: Richard Gong --- v2: this patch is added in patch set version 2 v3: change to put fpga_mgr node under

Re: [PATCH v3 6/9] trace_uprobe: Support SDT markers having reference count (semaphore)

Hi Ravi, sorry for delay! I am trying to recall what this code should do ;) At first glance, I do not see any serious problem in this version... except it doesn't apply to Linus's tree. just one question for now. On 04/17, Ravi Bangoria wrote: > > @@ -941,6 +1091,9 @@ typedef bool

Re: [PATCH v8 3/6] cpuset: Add cpuset.sched.load_balance flag to v2

On Thu, May 17, 2018 at 04:55:42PM -0400, Waiman Long wrote: > The sched.load_balance flag is needed to enable CPU isolation similar to > what can be done with the "isolcpus" kernel boot parameter. Its value > can only be changed in a scheduling domain with no child cpusets. On > a non-scheduling

Re: [PATCH v8 2/6] cpuset: Add new v2 cpuset.sched.domain flag

On Thu, May 17, 2018 at 04:55:41PM -0400, Waiman Long wrote: > A new cpuset.sched.domain boolean flag is added to cpuset v2. This new > flag indicates that the CPUs in the current cpuset should be treated > as a separate scheduling domain. The traditional name for this is a partition. >

Re: [PATCH v8 3/6] cpuset: Add cpuset.sched.load_balance flag to v2

On 05/24/2018 11:16 AM, Juri Lelli wrote: > On 24/05/18 11:09, Waiman Long wrote: >> On 05/24/2018 10:36 AM, Juri Lelli wrote: >>> On 17/05/18 16:55, Waiman Long wrote: >>> >>> [...] >>> + A parent cgroup cannot distribute all its CPUs to child + scheduling domain cgroups unless its

Re: [PATCH v8 3/6] cpuset: Add cpuset.sched.load_balance flag to v2

On 24/05/18 11:09, Waiman Long wrote: > On 05/24/2018 10:36 AM, Juri Lelli wrote: > > On 17/05/18 16:55, Waiman Long wrote: > > > > [...] > > > >> + A parent cgroup cannot distribute all its CPUs to child > >> + scheduling domain cgroups unless its load balancing flag is > >> + turned off. > >>

Re: [PATCH v8 3/6] cpuset: Add cpuset.sched.load_balance flag to v2

On 17/05/18 16:55, Waiman Long wrote: [...] > + A parent cgroup cannot distribute all its CPUs to child > + scheduling domain cgroups unless its load balancing flag is > + turned off. > + > + cpuset.sched.load_balance > + A read-write single value file which exists on non-root >

Re: [PATCH v2 0/7] mm: pages for hugetlb's overcommit may be able to charge to memcg

On Thu 24-05-18 21:58:49, TSUKADA Koutaro wrote: > On 2018/05/24 17:20, Michal Hocko wrote: > > On Thu 24-05-18 13:39:59, TSUKADA Koutaro wrote: > >> On 2018/05/23 3:54, Michal Hocko wrote: > > [...] > >>> I am also quite confused why you keep distinguishing surplus hugetlb > >>> pages from

Re: [PATCH] libata: remove ata_sff_data_xfer_noirq()

On 2018-05-07 17:52:16 [+0200], To Tejun Heo wrote: > On 2018-05-07 08:49:08 [-0700], Tejun Heo wrote: > > Hello, Sebastian. Hi Tejun, > > On Fri, May 04, 2018 at 05:06:20PM +0200, Sebastian Andrzej Siewior wrote: > > > ata_sff_data_xfer_noirq() is invoked via the ->sff_data_xfer hook. The > > >

Re: [PATCH v2 0/7] mm: pages for hugetlb's overcommit may be able to charge to memcg

On 2018/05/24 17:20, Michal Hocko wrote: > On Thu 24-05-18 13:39:59, TSUKADA Koutaro wrote: >> On 2018/05/23 3:54, Michal Hocko wrote: > [...] >>> I am also quite confused why you keep distinguishing surplus hugetlb >>> pages from regular preallocated ones. Being a surplus page is an >>>

Re: [PATCH 07/24] arm64: ilp32: add documentation on the ILP32 ABI for ARM64

Yury & Pavel, > On 24 May 2018, at 14:15, Yury Norov wrote: > > Hi Pavel, > > On Wed, May 23, 2018 at 04:06:20PM +0200, Pavel Machek wrote: >> On Wed 2018-05-16 11:18:52, Yury Norov wrote: >>> Based on Andrew Pinski's patch-series. >>> >>> Signed-off-by: Yury Norov

Re: [PATCH 07/24] arm64: ilp32: add documentation on the ILP32 ABI for ARM64

Hi Pavel, On Wed, May 23, 2018 at 04:06:20PM +0200, Pavel Machek wrote: > On Wed 2018-05-16 11:18:52, Yury Norov wrote: > > Based on Andrew Pinski's patch-series. > > > > Signed-off-by: Yury Norov > > So Andrew's signoff should be here? Yes it should, but it lost

Re: [PATCH v8 4/6] cpuset: Make generate_sched_domains() recognize isolated_cpus

On 24/05/18 10:04, Patrick Bellasi wrote: [...] > From 84bb8137ce79f74849d97e30871cf67d06d8d682 Mon Sep 17 00:00:00 2001 > From: Patrick Bellasi > Date: Wed, 23 May 2018 16:33:06 +0100 > Subject: [PATCH 1/1] cgroup/cpuset: disable sched domain rebuild when not >

Re: [PATCH v8 4/6] cpuset: Make generate_sched_domains() recognize isolated_cpus

On 17/05/18 16:55, Waiman Long wrote: [...] > @@ -849,7 +860,12 @@ static void rebuild_sched_domains_locked(void) >* passing doms with offlined cpu to partition_sched_domains(). >* Anyways, hotplug work item will rebuild sched domains. >*/ > - if

Re: [PATCH v8 4/6] cpuset: Make generate_sched_domains() recognize isolated_cpus

On 23-May 16:18, Waiman Long wrote: > On 05/23/2018 01:34 PM, Patrick Bellasi wrote: > > Hi Waiman, > > > > On 17-May 16:55, Waiman Long wrote: > > > > [...] > > > >> @@ -672,13 +672,14 @@ static int generate_sched_domains(cpumask_var_t > >> **domains, > >>int ndoms = 0; /* number of

Re: [PATCH v2 0/7] mm: pages for hugetlb's overcommit may be able to charge to memcg

On Thu 24-05-18 13:26:12, TSUKADA Koutaro wrote: [...] > I do not know if it is really a strong use case, but I will explain my > motive in detail. English is not my native language, so please pardon > my poor English. > > I am one of the developers for software that managing the resource used >

Re: [PATCH v2 0/7] mm: pages for hugetlb's overcommit may be able to charge to memcg

On Thu 24-05-18 13:39:59, TSUKADA Koutaro wrote: > On 2018/05/23 3:54, Michal Hocko wrote: [...] > > I am also quite confused why you keep distinguishing surplus hugetlb > > pages from regular preallocated ones. Being a surplus page is an > > implementation detail that we use for an internal

Re: [PATCH bpf-next v2 0/3] bpf: add boot parameters for sysctl knobs

On Wed, 23 May 2018 15:02:45 -0700 Alexei Starovoitov wrote: > On Wed, May 23, 2018 at 02:18:19PM +0200, Eugene Syromiatnikov wrote: > > Some BPF sysctl knobs affect the loading of BPF programs, and during > > system boot/init stages these sysctls are not yet

Re: [PATCH v2 1/5] PCI/AER: Define and allocate aer_stats structure for AER capable devices

On Wed, May 23, 2018 at 10:58:04AM -0700, Rajat Jain wrote: > --- > v2: Fix the license header as per Greg's suggestions > (Since there is disagreement with using "//" vs "/* */" for license > I decided to keep the one preferred by Linus, also used by others > in this directory) The