d support for V3s SoC")
> > Signed-off-by: Icenowy Zheng <icen...@aosc.io>
>
> Maxime,
> Ping. Have you checked this patchset?
Applied, thanks!
Maxime
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On Tue, Aug 22, 2017 at 01:14:09PM +0800, icen...@aosc.io wrote:
> 在 2017-08-21 17:34，Maxime Ripard 写道：
> > Hi,
> >
> > On Sun, Aug 20, 2017 at 01:29:57PM +0800, Icenowy Zheng wrote:
> > > Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
&g
onst sun8i_board_dt_compat[] = {
> "allwinner,sun8i-h2-plus",
> "allwinner,sun8i-h3",
> "allwinner,sun8i-v3s",
> + "allwinner,sun8i-r40",
And same thing here.
Thanks!
Maxime
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On Thu, May 04, 2017 at 10:45:11PM +0800, Icenowy Zheng wrote:
>
>
> 于 2017年5月4日 GMT+08:00 下午10:41:52, Maxime Ripard
> <maxime.rip...@free-electrons.com> 写到:
> >On Thu, May 04, 2017 at 10:03:26PM +0800, Icenowy Zheng wrote:
> >>
> >>
> >&
pinctrl-names = "default";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c1: i2c@1c2b000 {
> +
On Thu, May 04, 2017 at 10:07:47PM +0800, Icenowy Zheng wrote:
>
>
> 于 2017年5月4日 GMT+08:00 下午10:04:31, Maxime Ripard
> <maxime.rip...@free-electrons.com> 写到:
> >On Thu, May 04, 2017 at 09:49:58PM +0800, Icenowy Zheng wrote:
> >> Allwinner A10, A20 and
regulator-max-microvolt = <130>;
> + regulator-name = "vdd-sys";
> +};
> +
> +_dcdc5 {
> + regulator-always-on;
> + regulator-min-microvolt = <150>;
> + regulator-max-microvolt = <150>;
> + regulator-name = "vcc-dram";
> +};
> +
> +_dldo1 {
> + regulator-min-microvolt = <180>;
> + regulator-max-microvolt = <330>;
> + regulator-name = "vcc-wifi-io";
> +};
> +
> +_dldo2 {
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + regulator-name = "vcc-wifi";
> +};
> +
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins>;
If there is multiple options, then it should be suffixed. If there's
only a single option, then it should be set in the DTSI. Either way,
this is wrong.
Maxime
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On Thu, May 04, 2017 at 10:03:26PM +0800, Icenowy Zheng wrote:
>
>
> 于 2017年5月4日 GMT+08:00 下午10:02:20, Maxime Ripard
> <maxime.rip...@free-electrons.com> 写到:
> >On Thu, May 04, 2017 at 09:49:59PM +0800, Icenowy Zheng wrote:
> >> static const struct of_
US_UART0] = { 0x2d8, BIT(16) },
> + [RST_BUS_UART1] = { 0x2d8, BIT(17) },
> + [RST_BUS_UART2] = { 0x2d8, BIT(18) },
> + [RST_BUS_UART3] = { 0x2d8, BIT(19) },
> + [RST_BUS_UART4] = { 0x2d8, BIT(20) },
> + [RST_BUS_UART5] = { 0x2d8, BIT(21) },
> + [RST_BUS_UART6] = { 0x2d8, BIT(22) },
> + [RST_BUS_UART7] = { 0x2d8, BIT(23) },
> +};
> +
> +static const struct sunxi_ccu_desc sun8i_r40_ccu_desc = {
> + .ccu_clks = sun8i_r40_ccu_clks,
> + .num_ccu_clks = ARRAY_SIZE(sun8i_r40_ccu_clks),
> +
> + .hw_clks= _r40_hw_clks,
> +
> + .resets = sun8i_r40_ccu_resets,
> + .num_resets = ARRAY_SIZE(sun8i_r40_ccu_resets),
> +};
> +
> +static struct ccu_mux_nb sun8i_r40_cpu_nb = {
> + .common = _clk.common,
> + .cm = _clk.mux,
> + .delay_us = 1, /* > 8 clock cycles at 24 MHz */
> + .bypass_index = 1, /* index of 24 MHz oscillator */
> +};
> +
> +static void __init sun8i_r40_ccu_setup(struct device_node *node)
> +{
> + void __iomem *reg;
> + u32 val;
> +
> + reg = of_io_request_and_map(node, 0, of_node_full_name(node));
> + if (IS_ERR(reg)) {
> + pr_err("%s: Could not map the clock registers\n",
> +of_node_full_name(node));
> + return;
> + }
> +
> + /* Force the PLL-Audio-1x divider to 4 */
> + val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
> + val &= ~GENMASK(19, 16);
> + writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
> +
> + sunxi_ccu_probe(node, reg, _r40_ccu_desc);
> +
> + ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
> + _r40_cpu_nb);
Did you test cpufreq on it? IT's likely to miss the gating notifier...
Maxime
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commit title is misleading since
you're not adding it to the A10 driver. You just adding SoC IDs
definitions
Maxime
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for the same
device: this driver, and the old one. This is not ok, and probably
introduces some corner cases.
Maxime
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yz>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Thanks,
Maxime
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ased on my
current branch.
Fixed the conflicts and applied.
Maxime
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On Fri, Jan 20, 2017 at 01:54:46AM +0800, Icenowy Zheng wrote:
> Allwinner V3s is now driven by sunxi-ng CCU driver.
>
> Add devicetree binding for it.
>
> Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
Applied. Thanks,
Maxime
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Embe
<icen...@aosc.xyz>
> ---
Having a changelog somewhere would help. Why did you drop your cover
letter?
> +static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
> "pll-ddr" };
This is more that 80 characters and triggers a warning in
chec
;
> + };
Did you have the chance to actually test how the RTC was behaving?
Other RTC have been pretty bad at keeping time, this is probably
something you want to check.
Applied,
Maxime
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pplied, thanks
Maxime
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On Wed, Jan 18, 2017 at 01:02:03AM +0800, Icenowy Zheng wrote:
>
> 2017年1月17日 17:04于 Maxime Ripard <maxime.rip...@free-electrons.com>写道：
> >
> > Hi,
> >
> > On Tue, Jan 17, 2017 at 02:01:14AM +0800, Icenowy Zheng wrote:
> > > V3s has a similar but
On Wed, Jan 18, 2017 at 01:08:14AM +0800, Icenowy Zheng wrote:
>
>
> 17.01.2017, 17:05, "Maxime Ripard" <maxime.rip...@free-electrons.com>:
> > Hi,
> >
> > On Tue, Jan 17, 2017 at 02:01:14AM +0800, Icenowy Zheng wrote:
> >> V3s has a si
nxi.org wiki hosted address of V3s datasheet.
>
> Note: the V3s datasheet contains its user manual.
That would be great to use User Manual in the filename rather than
datasheet then. The datasheet is something different.
Maxime
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uot;
> to "pll-video")
> - Clocks about CSI largely differs. (As V3s is designed as a camera SoC, and
> it have an extra "pll-isp")
OK.
Thanks,
Maxime
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Hi,
On Wed, Jan 11, 2017 at 11:55:16AM +0800, Icenowy Zheng wrote:
>
> 2017年1月11日 02:10于 Maxime Ripard <maxime.rip...@free-electrons.com>写道：
> >
> > On Tue, Jan 03, 2017 at 11:16:26PM +0800, Icenowy Zheng wrote:
> > > V3s has a similar but cut-down CCU
On Thu, Jan 12, 2017 at 03:44:53AM +0800, Icenowy Zheng wrote:
>
>
> 12.01.2017, 03:40, "Icenowy Zheng" <icen...@aosc.xyz>:
> > 11.01.2017, 02:10, "Maxime Ripard" <maxime.rip...@free-electrons.com>:
> >> On Tue, Jan 03, 2017 at 11:16:26
On Tue, Jan 03, 2017 at 11:16:27PM +0800, Icenowy Zheng wrote:
> V3s SoC features only a pin controller (for the lack of CPUs part).
>
> Add a driver for this controller.
>
> Signed-off-by: Icenowy Zheng <icen...@aosc.xyz>
Acked-by: Maxime Ripard <maxime.rip...@fre
as-pull-up;
Why do you need a pullup here?
Looks good otherwise.
Thanks!
Maxime
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c-datasheet
> +
Please don't put random links in there, but at least something that we
know will be there in a couple of weeks/monthes/years
Thanks,
Maxime
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On Mon, Dec 05, 2016 at 07:01:46PM +0800, Icenowy Zheng wrote:
>
>
> 05.12.2016, 17:40, "Maxime Ripard" <maxime.rip...@free-electrons.com>:
> > On Mon, Dec 05, 2016 at 04:59:44PM +0800, Icenowy Zheng wrote:
> >> 2016年12月5日 16:52于 Maxime Rip
On Fri, Dec 02, 2016 at 04:10:46PM +, Andre Przywara wrote:
> Hi,
>
> On 02/12/16 14:32, Icenowy Zheng wrote:
> >
> >
> > 02.12.2016, 22:30, "Hans de Goede" <hdego...@redhat.com>:
> >> Hi,
> >>
> >> On 02-12-1
e...@aosc.xyz
Please make sure to disable the HTML replies, this is what your mail
looks like on a !HTML MUA :)
Maxime
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On Mon, Dec 05, 2016 at 04:59:44PM +0800, Icenowy Zheng wrote:
>
> 2016年12月5日 16:52于 Maxime Ripard <maxime.rip...@free-electrons.com>写道：
> >
> > On Fri, Dec 02, 2016 at 10:22:30PM +0800, Icenowy Zheng wrote:
> > >
> > >
> > > 01.12.2016, 17:36
{
> + status = "okay";
> +};
> +
> + {
> + leds_opi0: led_pins@0 {
> + pins = "PA17";
> + function = "gpio_out";
> + };
> +};
> +
> +_pio {
> + leds_r_opi0: led_pins@0 {
> + pins = "PL10";
> + function = "gpio_out";
> + };
> +};
> +
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins_a>;
> + status = "okay";
> +};
> +
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins>;
> + status = "disabled";
> +};
> +
> + {
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins>;
> + status = "disabled";
> +};
I'm not sure you answered me on this one. Are those exposed on the
headers? why did you put them as disabled here?
Thanks!
Maxime
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; @@ -104,6 +136,11 @@
> pins = "PA17";
> function = "gpio_out";
> };
> +
> + vcc_wifi_pin_opi0: vcc_wifi_pin@0 {
> + allwinner,pins = "PA20";
This should be pins
> + allwinner,function = "gpio_out&
ings/arm/sunxi.txt
> index 4d6467c..26b35a7 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> @@ -13,6 +13,7 @@ using one of the following compatible strings:
>allwinner,sun8i-a33
>allwinner,sun8i-a83t
>
DC-in jack. So IMHO adding something like
> the fixed reg_vcc5v0 a supply here just makes the dt
> harder to read.
It also makes the regulator tree more complete and accurate because
you'd list all the devices that are needing those regulators. That
would also make it easier to deal with in th
DTSI in your board. We'll
create it if we need it at some point.
Maxime
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allwinner,pins = "PL10";
> + allwinner,function = "gpio_out";
> + allwinner,drive = ;
> + allwinner,pull = ;
You can drop the drive and pull properties, and could you use the
generic pins and function properties for those nodes?
arm/sunxi.txt
> @@ -13,5 +13,6 @@ using one of the following compatible strings:
>allwinner,sun8i-a33
>allwinner,sun8i-a83t
>allwinner,sun8i-h3
> + allwinner,sun8i-h2plus
That's a nitpick, but I'd prefer to have sun8i-h2-plus.
Thanks!
Maxime
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On Wed, Feb 24, 2016 at 06:45:53PM +0530, Laxman Dewangan wrote:
> Use devm_pinctrl_register() for pin control registration and clean
> the error path.
>
> Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com>
> Cc: Maxime Ripard <maxime.rip...@free-electrons.co
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