Re: [PATCH v3 04/15] ARM: dts: dra74x-mmc-iodelay: Add a new pinctrl group for clk line without pullup

* Kishon Vijay Abraham I [180425 12:57]: > --- a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi > +++ b/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi > @@ -49,6 +49,17 @@ > >; > }; > > + mmc1_pins_default_no_clk_pu: mmc1_pins_default_no_clk_pu { > +

Re: [PATCH 00/41] omap_hsmmc: Add ADMA support and UHS/HS200/DDR support

Hi, * Kishon Vijay Abraham I [170519 01:19]: > This series adds UHS, HS200, DDR mode and ADMA support to > omap_hsmmc driver used to improve the throughput of MMC/SD in dra7 > SoCs. Certainly seems way less intrusive than earlier before the dmaengine changes :) > *) tuning ratio

Re: [PATCH 37/37] ARM: dts: DRA7: Add pcie1 dt node for EP mode

* Kishon Vijay Abraham I [170112 02:34]: > Add pcie1 dt node in order for the controller to operate in > endpoint mode. However since none of the dra7 based boards have > slots configured to operate in endpoint mode, keep EP mode > disabled. Can this be merged separately later on

Re: [PATCH 36/37] ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP

* Kishon Vijay Abraham I <kis...@ti.com> [170115 22:06]: > Hi Tony, > > On Friday 13 January 2017 10:45 PM, Tony Lindgren wrote: > > * Kishon Vijay Abraham I <kis...@ti.com> [170112 02:35]: > >> The PCIe programming sequence in TRM suggests CLKSTCTRL o

Re: [PATCH 36/37] ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP

* Kishon Vijay Abraham I [170112 02:35]: > The PCIe programming sequence in TRM suggests CLKSTCTRL of PCIe should > be set to SW_WKUP. There are no issues when CLKSTCTRL is set to HW_AUTO > in RC mode. However in EP mode, the host system is not able to access the > MEMSPACE and