[PATCH v2 7/7] tools: PCI: Add MSI-X support

Add MSI-X support to pcitest tool. Add 2 new IOCTL commands: - Allow to reconfigure driver IRQ type in runtime. - Allow to retrieve current driver IRQ type configured. Modify pcitest.sh script to accommodate MSI-X interrupt tests. Signed-off-by: Gustavo Pimentel

[PATCH v2 5/7] PCI: dwc: Add legacy interrupt callback handler

Add a legacy interrupt callback handler. Currently DesignWare IP don't allow trigger legacy interrupts. Signed-off-by: Gustavo Pimentel --- Change v1->v2: - Nothing changed, just to follow the patch set version. drivers/pci/dwc/pcie-designware-ep.c | 10

[PATCH v2 6/7] misc: pci_endpoint_test: Add MSI-X support

Add MSI-X support and update driver documentation accordingly. Add new driver parameter to allow interruption type selection. Add 2 new IOCTL commands: - Allow to reconfigure driver IRQ type in runtime. - Allow to retrieve current driver IRQ type configured. Change Legacy/MSI/MSI-X test

[PATCH v2 0/7] Add MSI-X support on pcitest tool

Patch series made against Lorenzo's branches and also depends of: - pci/dwc - pci/endpoint Add MSI-X support on pcitest tool. Add new callbacks methods and handlers to trigger the MSI-X interrupts on the EP DesignWare IP driver. Allow to set/get MSI-X EP maximum capability number. Rework on

[PATCH v2 4/7] PCI: dwc: Rework MSI callbacks handler

Remove duplicate defines located on pcie-designware.h file already available on /include/uapi/linux/pci-regs.h file. Add pci_epc_set_msi() maximum 32 interrupts validation. Signed-off-by: Gustavo Pimentel --- Change v1->v2: - Nothing changed, just to follow the

[PATCH v2 1/7] PCI: endpoint: Add MSI-X interfaces

Add PCI_EPC_IRQ_MSIX type. Add MSI-X callbacks signatures to the ops structure. Add sysfs interface for set/get MSI-X capability maximum number. Change pci_epc_raise_irq() signature, namely the interrupt_num variable type from u8 to u16 to accommodate 2048 maximum MSI-X interrupts.

[PATCH v2 3/7] PCI: cadence: Update cdns_pcie_ep_raise_irq function signature

Change cdns_pcie_ep_raise_irq() signature, namely the interrupt_num variable type from u8 to u16 to accommodate 2048 maximum MSI-X interrupts. Signed-off-by: Gustavo Pimentel Acked-by: Alan Douglas --- Change v1->v2: - Nothing changed, just

Re: [PATCH] kvm: rename HINTS_DEDICATED to KVM_HINTS_REALTIME

On 17/05/2018 16:54, Michael S. Tsirkin wrote: > HINTS_DEDICATED seems to be somewhat confusing: > > Guest doesn't really care whether it's the only task running on a host > CPU as long as it's not preempted. > > And there are more reasons for Guest to be preempted than host CPU > sharing, for

[PATCH] kvm: rename HINTS_DEDICATED to KVM_HINTS_REALTIME

HINTS_DEDICATED seems to be somewhat confusing: Guest doesn't really care whether it's the only task running on a host CPU as long as it's not preempted. And there are more reasons for Guest to be preempted than host CPU sharing, for example, with memory overcommit it can get preempted on a

Re: [PATCH 0/7] i2c: clean up include/linux/i2c-*

On Thu, Apr 19, 2018 at 10:00:06PM +0200, Wolfram Sang wrote: > Move all plain platform_data includes to the platform_data-dir > (except for i2c-pnx which can be moved into the driver itself). > > My preference is to take these patches via the i2c tree. I can provide an > immutable branch if

Re: [PATCH v5 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

On 16/05/2018 05:55, Ganapatrao Kulkarni wrote: This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory Controller(DMC) and Level 3 Cache(L3C). Hi, Just some coding comments below: ThunderX2 has 8 independent DMC PMUs to capture performance events corresponding to 8 channels

Re: [PATCH v4 19/31] Documentation: kconfig: document a new Kconfig macro language

2018-05-17 15:38 GMT+09:00 Kees Cook : > On Wed, May 16, 2018 at 11:16 PM, Masahiro Yamada > wrote: >> Add a document for the macro language introduced to Kconfig. >> >> The motivation of this work is to move the compiler option tests to >>

Re: [PATCH v4 19/31] Documentation: kconfig: document a new Kconfig macro language

On Wed, May 16, 2018 at 11:16 PM, Masahiro Yamada wrote: > Add a document for the macro language introduced to Kconfig. > > The motivation of this work is to move the compiler option tests to > Kconfig from Makefile. A number of kernel features require the >

Re: [PATCH v2] coresight: documentation: update sysfs section

On Wed, 16 May 2018 13:18:23 -0600 Jonathan Corbet wrote: > On Mon, 14 May 2018 12:19:59 -0500 > Kim Phillips wrote: > > > - Align and show updated ls devices output from the TC2, based on > > current driver > > > > - Provide an example from an ETMv4

Re: [PATCH v2] coresight: documentation: update sysfs section

On Mon, 14 May 2018 12:19:59 -0500 Kim Phillips wrote: > - Align and show updated ls devices output from the TC2, based on > current driver > > - Provide an example from an ETMv4 based system (Juno) > > - Reflect changes to the way the RAM write pointer is accessed

Re: [PATCH] Documentation: gpio: driver: Fix a typo and some odd grammar

On Wed, 16 May 2018 14:08:00 +0200 Jonathan Neuschäfer wrote: > Signed-off-by: Jonathan Neuschäfer Applied, thanks. jon -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org

[PATCH] Documentation: gpio: driver: Fix a typo and some odd grammar

Signed-off-by: Jonathan Neuschäfer --- Documentation/driver-api/gpio/driver.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/driver-api/gpio/driver.rst b/Documentation/driver-api/gpio/driver.rst index 505ee906d7d9..cbe0242842d1

[PATCH v9 00/24] ILP32 for ARM64

This series enables AARCH64 with ILP32 mode. As supporting work, it introduces ARCH_32BIT_OFF_T configuration option that is enabled for existing 32-bit architectures but disabled for new arches (so 64-bit off_t userspace type is used by new userspace). Also it deprecates getrlimit and setrlimit

[PATCH 02/24] ptrace: Add compat PTRACE_{G,S}ETSIGMASK handlers

From: James Morse compat_ptrace_request() lacks handlers for PTRACE_{G,S}ETSIGMASK, instead using those in ptrace_request(). The compat variant should read a compat_sigset_t from userspace instead of ptrace_request()s sigset_t. While compat_sigset_t is the same size as

[PATCH 03/24] compat ABI: use non-compat openat and open_by_handle_at variants

The only difference between native and compat openat and open_by_handle_at is that non-compat version forces O_LARGEFILE, and it should be the default behaviour for all architectures, as we are going to drop the support of 32-bit userspace off_t. The exception is tile32 that continues with compat

[PATCH 01/24] arm64: signal: Make parse_user_sigframe() independent of rt_sigframe layout

From: Dave Martin ILP32 uses the same struct sigcontext as the native ABI (i.e., LP64), but a different layout for the rest of the signal frame (since siginfo_t and ucontext_t are both ABI-dependent). Since the purpose of parse_user_sigframe() is really to parse sigcontext

[PATCH 09/24] arm64: rename functions that reference compat term

The ILP32 for ARM64 patch series introduces another 'compat' mode for arm64. So to avoid confusing, aarch32-only functions renamed in according to it. Signed-off-by: Yury Norov --- arch/arm64/include/asm/ptrace.h | 10 ++-- arch/arm64/include/asm/signal32.h|

[PATCH 10/24] arm64: uapi: set __BITS_PER_LONG correctly for ILP32 and LP64

From: Andrew Pinski Define __BITS_PER_LONG depending on the ABI used (i.e. check whether __ILP32__ or __LP64__ is defined). This is necessary for glibc to determine the appropriate type definitions for the system call interface. Signed-off-by: Andrew Pinski

[PATCH 11/24] arm64: introduce is_a32_task and is_a32_thread (for AArch32 compat)

Based on patch of Andrew Pinski. This patch introduces is_a32_compat_task and is_a32_thread so it is easier to say this is a a32 specific thread or a generic compat thread/task. Corresponding functions are located in to avoid mess in headers. Some files include both and , and this is wrong

[PATCH 14/24] arm64: change compat_elf_hwcap and compat_elf_hwcap2 prefix to a32

ILP32 patch series introduces new type of binaries which is also compat. So rename existung aarch32 compat_elf_hwcap's helps to avoid confusing. Signed-off-by: Yury Norov --- arch/arm64/include/asm/hwcap.h | 2 +- arch/arm64/kernel/binfmt_elf32.c | 4 ++--

[PATCH 12/24] arm64: ilp32: add is_ilp32_compat_{task,thread} and TIF_32BIT_AARCH64

ILP32 tasks are needed to be distinguished from LP64 and AARCH32. This patch adds helper functions is_ilp32_compat_{task,thread} and thread flag TIF_32BIT_AARCH64 to address it. This is a preparation for following patches in ILP32 patchset. For consistency, SET_PERSONALITY is changed here

[PATCH 16/24] arm64: ilp32: share aarch32 syscall handlers

According to userspace/kernel ABI, userspace off_t is passed in register pair just like in aarch32. In this patch corresponding aarch32 handlers are shared to ilp32 code. Signed-off-by: Yury Norov --- arch/arm64/kernel/Makefile | 1 +

[PATCH 15/24] arm64: ilp32: introduce binfmt_ilp32.c

Like binfmt_elf32.c for AARCH32, binfmt_ilp32.c is needed to handle ILP32 binaries. Signed-off-by: Yury Norov Signed-off-by: Bamvor Jian Zhang --- arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/binfmt_ilp32.c | 87

[PATCH 19/24] arm64: signal32: move ilp32 and aarch32 common code to separated file

ILP32 needs to mix 32bit struct siginfo and 64bit sigframe for its signal handlers. Move the existing compat code for copying siginfo to user space and manipulating signal masks into signal32_common.c so it can be used to deliver aarch32 and ilp32 signals. Signed-off-by: Yury Norov

[PATCH 17/24] arm64: ilp32: add sys_ilp32.c and a separate table (in entry.S) to use it

From: Andrew Pinski Add a separate syscall-table for ILP32, which dispatches either to native LP64 system call implementation or to compat-syscalls, as appropriate. Signed-off-by: Andrew Pinski Signed-off-by: Yury Norov

[PATCH 20/24] arm64: ilp32: introduce ilp32-specific sigframe and ucontext

From: Yury Norov ILP32 uses AARCH32 compat structures and syscall handlers for signals. But ILP32 rt_sigframe and ucontext structures differ from both LP64 and AARCH32. >From software point of view ILP32 is typical 32-bit compat ABI, and from hardware point of view,

[PATCH 18/24] arm64: signal: share lp64 signal structures and routines to ilp32

Following patches of the series introduce ILP32-specific structures and handlers for signal subsystem. In this patch, functions and structures that common for LP64 and ILP32 are moved to arch/arm64/include/asm/signal_common.h to let ILP32 code reuse them. Some functions work with struct

[PATCH 22/24] arm64:ilp32: add vdso-ilp32 and use for signal return

From: Philipp Tomsich ILP32 VDSO exports following symbols: __kernel_rt_sigreturn; __kernel_gettimeofday; __kernel_clock_gettime; __kernel_clock_getres. What shared object to use, kernel selects depending on result of is_ilp32_compat_task() in

[PATCH 23/24] arm64:ilp32: add ARM64_ILP32 to Kconfig

From: Andrew Pinski This patch adds the config option for ILP32. Signed-off-by: Andrew Pinski Signed-off-by: Philipp Tomsich Signed-off-by: Christoph Muellner

[PATCH 24/24] arm64: ilp32: Make the Kconfig option default y

From: Catalin Marinas The intention of the ILP32 branches is to enable ILP32 by default. This default is to be revisited for upstream merging. Signed-off-by: Catalin Marinas Signed-off-by: Yury Norov ---

[PATCH 21/24] arm64: ptrace: handle ptrace_request differently for aarch32 and ilp32

ILP32 has context-related structures different from both aarch32 and aarch64/lp64. In this patch compat_arch_ptrace() renamed to compat_a32_ptrace(), and compat_arch_ptrace() only makes choice between compat_a32_ptrace() and new compat_ilp32_ptrace() handler. compat_ilp32_ptrace() calls generic

[PATCH 13/24] arm64: introduce binfmt_elf32.c

As we support more than one compat formats, it looks more reasonable to not use fs/compat_binfmt.c. Custom binfmt_elf32.c allows to move aarch32 specific definitions there and make code more maintainable and readable. Signed-off-by: Yury Norov --- arch/arm64/Kconfig

[PATCH 07/24] arm64: ilp32: add documentation on the ILP32 ABI for ARM64

Based on Andrew Pinski's patch-series. Signed-off-by: Yury Norov --- Documentation/arm64/ilp32.txt | 45 +++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/arm64/ilp32.txt diff --git a/Documentation/arm64/ilp32.txt

[PATCH 08/24] arm64: rename COMPAT to AARCH32_EL0 in Kconfig

From: Andrew Pinski In this patchset ILP32 ABI support is added. Additionally to AARCH32, which is binary-compatible with ARM, ILP32 is (mostly) ABI-compatible. >From now, AARCH32_EL0 (former COMPAT) config option means the support of AARCH32 userspace, and ARM64_ILP32 -

[PATCH 04/24] 32-bit userspace ABI: introduce ARCH_32BIT_OFF_T config option

All new 32-bit architectures should have 64-bit userspace off_t type, but existing architectures has 32-bit ones. To enforce the rule, new config option is added to arch/Kconfig that defaults ARCH_32BIT_OFF_T to be disabled for new 32-bit architectures. All existing 32-bit architectures enable it

[PATCH 06/24] thread: move thread bits accessors to separated file

Thread bits may be accessed from low-level code, so isolating is a measure to avoid circular dependencies in header files. The exact reason for circular dependency is WARN_ON() macro added in patch edd63a27 "set_restore_sigmask() is never called without SIGPENDING (and never should be)"

[PATCH v5 0/2] Add ThunderX2 SoC Performance Monitoring Unit driver

This patchset adds PMU driver for Cavium's ThunderX2 SoC UNCORE devices. The SoC has PMU support in L3 cache controller (L3C) and in the DDR4 Memory Controller (DMC). v5: -Incroporated review comments from Mark Rutland[2] v4: -Incroporated review comments from Mark Rutland[1] [1]

[PATCH v5 1/2] perf: uncore: Adding documentation for ThunderX2 pmu uncore driver

Documentation for the UNCORE PMUs on Cavium's ThunderX2 SoC. The SoC has PMU support in its L3 cache controller (L3C) and in the DDR4 Memory Controller (DMC). Signed-off-by: Ganapatrao Kulkarni --- Documentation/perf/thunderx2-pmu.txt | 66

Re: [PATCH v9 00/24] ILP32 for ARM64

Hi all, On Tue, May 15, 2018 at 10:11:50PM +0300, Yury Norov wrote: > This series enables AARCH64 with ILP32 mode. > > As supporting work, it introduces ARCH_32BIT_OFF_T configuration > option that is enabled for existing 32-bit architectures but disabled > for new arches (so 64-bit off_t

[PATCH 01/24] arm64: signal: Make parse_user_sigframe() independent of rt_sigframe layout

From: Dave Martin ILP32 uses the same struct sigcontext as the native ABI (i.e., LP64), but a different layout for the rest of the signal frame (since siginfo_t and ucontext_t are both ABI-dependent). Since the purpose of parse_user_sigframe() is really to parse sigcontext

[PATCH 02/24] ptrace: Add compat PTRACE_{G,S}ETSIGMASK handlers

From: James Morse compat_ptrace_request() lacks handlers for PTRACE_{G,S}ETSIGMASK, instead using those in ptrace_request(). The compat variant should read a compat_sigset_t from userspace instead of ptrace_request()s sigset_t. While compat_sigset_t is the same size as

[PATCH v9 00/24] ILP32 for ARM64

This series enables AARCH64 with ILP32 mode. As supporting work, it introduces ARCH_32BIT_OFF_T configuration option that is enabled for existing 32-bit architectures but disabled for new arches (so 64-bit off_t userspace type is used by new userspace). Also it deprecates getrlimit and setrlimit

Re: [PATCH v3] coresight: documentation: update sysfs section

On 14 May 2018 at 13:18, Kim Phillips wrote: > - Align and show updated ls devices output from the TC2, based on > current driver > > - Provide an example from an ETMv4 based system (Juno) > > - Reflect changes to the way the RAM write pointer is accessed since > it got

Re: [PATCH v2 11/11] docs: fix broken references with multiple hints

On Wed, 9 May 2018 10:18:54 -0300 Mauro Carvalho Chehab wrote: > diff --git a/Documentation/trace/events.rst b/Documentation/trace/events.rst > index 7b6b1236ec2e..c292117b83a9 100644 > --- a/Documentation/trace/events.rst > +++ b/Documentation/trace/events.rst > @@

[PATCH v12 1/4] arm64: KVM: export the capability to set guest SError syndrome

For the arm64 RAS Extension, user space can inject a virtual-SError with specified ESR. So user space needs to know whether KVM support to inject such SError, this interface adds this query for this capability. KVM will check whether system support RAS Extension, if supported, KVM returns true to

[PATCH v12 4/4] arm64: handle NOTIFY_SEI notification by the APEI driver

Add a helper to handle the NOTIFY_SEI notification, when kernel gets the NOTIFY_SEI notification, call this helper and let APEI driver to handle this notification. Signed-off-by: Dongjiu Geng --- arch/arm64/include/asm/system_misc.h | 1 + arch/arm64/kernel/traps.c

[PATCH v12 2/4] arm/arm64: KVM: Add KVM_GET/SET_VCPU_EVENTS

For the migrating VMs, user space may need to know the exception state. For example, in the machine A, KVM make an SError pending, when migrate to B, KVM also needs to pend an SError. This new IOCTL exports user-invisible states related to SError. Together with appropriate user space changes,

[PATCH v12 0/4] set VSESR_EL2 by user space and support NOTIFY_SEI notification

1. Detect whether KVM can set set guest SError syndrome 2. Support to Set VSESR_EL2 and inject SError by user space. 3. Support live migration to keep SError pending state and VSESR_EL2 value. 4. ACPI 6.1 adds support for NOTIFY_SEI as a GHES notification mechanism, so support this

[PATCH v12 3/4] ACPI / APEI: Add SEI notification type support for ARMv8

ACPI 6.x adds support for NOTIFY_SEI as a GHES notification mechanism, so add new GHES notification handling functions. Expose API ghes_notify_sei() to arch code, arch code will call this API when it gets this NOTIFY_SEI. Signed-off-by: Dongjiu Geng Note: Firmware will

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

Hi Mark, On Sat, May 5, 2018 at 12:16 AM, Ganapatrao Kulkarni wrote: > Hi Mark, > > On Thu, Apr 26, 2018 at 4:29 PM, Mark Rutland wrote: >> Hi, >> >> On Wed, Apr 25, 2018 at 02:30:47PM +0530, Ganapatrao Kulkarni wrote: >>> + >>> +/* L3c and DMC has 16

Re: [PATCH v2 11/11] docs: fix broken references with multiple hints

On Wednesday, May 09, 2018 10:18:54 AM Mauro Carvalho Chehab wrote: > The script: > ./scripts/documentation-file-ref-check --fix-rst > > Gives multiple hints for broken references on some files. > Manually use the one that applies for some files. > > Signed-off-by: Mauro Carvalho Chehab

Re: [PATCH 14/18] fbdev: modedb.c: fix a kernel-doc markup

On Monday, May 07, 2018 06:35:50 AM Mauro Carvalho Chehab wrote: > Use code blocks to avoid those warnings and make it look nicer. > > ./drivers/video/fbdev/core/modedb.c:647: WARNING: Inline strong > start-string without end-string. > ./drivers/video/fbdev/core/modedb.c:647:

Re: [bpf-next PATCH 0/5] bpf, doc: convert Documentation/bpf to RST-formatting

On Mon, May 14, 2018 at 10:57:25PM -0700, Y Song wrote: > On Mon, May 14, 2018 at 6:42 AM, Jesper Dangaard Brouer > wrote: > > The kernel is moving files under Documentation to use the RST > > (reStructuredText) format and Sphinx [1]. This patchset converts the > > files under

Re: [bpf-next PATCH 0/5] bpf, doc: convert Documentation/bpf to RST-formatting

On Mon, May 14, 2018 at 6:42 AM, Jesper Dangaard Brouer wrote: > The kernel is moving files under Documentation to use the RST > (reStructuredText) format and Sphinx [1]. This patchset converts the > files under Documentation/bpf/ into RST format. The Sphinx > integration is

[PATCH] Documentation: arm: clean up Marvell Berlin family info

Remove dead links, make spacing consistent, and note that the family was acquired by Synaptics in 2017. Signed-off-by: Thomas Hebb --- Documentation/arm/Marvell/README | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-) diff --git

Re: [PATCH v3] coresight: documentation: update sysfs section

On 05/14/2018 12:18 PM, Kim Phillips wrote: > - Align and show updated ls devices output from the TC2, based on > current driver > > - Provide an example from an ETMv4 based system (Juno) > > - Reflect changes to the way the RAM write pointer is accessed since > it got changed in commit

Re: [PATCH 10/18] rcu: rcupdate.h: get rid of Sphinx warnings at rcu_pointer_handoff()

On Wed, May 09, 2018 at 08:55:33AM -0300, Mauro Carvalho Chehab wrote: > Em Mon, 7 May 2018 07:23:22 -0700 > "Paul E. McKenney" escreveu: > > > On Mon, May 07, 2018 at 06:35:46AM -0300, Mauro Carvalho Chehab wrote: > > > The code example at rcupdate.h currently

[PATCH v3] coresight: documentation: update sysfs section

- Align and show updated ls devices output from the TC2, based on current driver - Provide an example from an ETMv4 based system (Juno) - Reflect changes to the way the RAM write pointer is accessed since it got changed in commit 7d83d17795ef ("coresight: tmc: adding sysFS management

Re: [PATCH v2] coresight: documentation: update sysfs section

On 05/14/2018 10:19 AM, Kim Phillips wrote: > - Align and show updated ls devices output from the TC2, based on > current driver > > - Provide an example from an ETMv4 based system (Juno) > > - Reflect changes to the way the RAM write pointer is accessed since > it got changed in commit

[PATCH v2] coresight: documentation: update sysfs section

- Align and show updated ls devices output from the TC2, based on current driver - Provide an example from an ETMv4 based system (Juno) - Reflect changes to the way the RAM write pointer is accessed since it got changed in commit 7d83d17795ef ("coresight: tmc: adding sysFS management

Re: [bpf-next PATCH 5/5] bpf, doc: howto use/run the BPF selftests

On Mon, 14 May 2018 17:15:54 +0200 Silvan Jegen wrote: > Hi > > Some typo fixes below. > > On Mon, May 14, 2018 at 3:43 PM Jesper Dangaard Brouer > wrote: > > I always forget howto run the BPF selftests. Thus, lets add that info > > to the QA document.

Re: [bpf-next PATCH 5/5] bpf, doc: howto use/run the BPF selftests

Hi Some typo fixes below. On Mon, May 14, 2018 at 3:43 PM Jesper Dangaard Brouer wrote: > I always forget howto run the BPF selftests. Thus, lets add that info > to the QA document. > Documentation was based on Cilium's documentation: >

[bpf-next PATCH 3/5] bpf, doc: convert bpf_design_QA.rst to use RST formatting

The RST formatting is done such that that when rendered or converted to different formats, an automatic index with links are created to the subsections. Thus, the questions are created as sections (or subsections), in-order to get the wanted auto-generated FAQ/QA index. Special thanks to Quentin

[bpf-next PATCH 5/5] bpf, doc: howto use/run the BPF selftests

I always forget howto run the BPF selftests. Thus, lets add that info to the QA document. Documentation was based on Cilium's documentation: http://cilium.readthedocs.io/en/latest/bpf/#verifying-the-setup Signed-off-by: Jesper Dangaard Brouer ---

[bpf-next PATCH 4/5] bpf, doc: convert bpf_devel_QA.rst to use RST formatting

Same story as bpf_design_QA.rst RST format conversion. Again thanks to Quentin Monnet for fixes and patches that have been squashed. Signed-off-by: Jesper Dangaard Brouer --- Documentation/bpf/bpf_devel_QA.rst | 799

[bpf-next PATCH 2/5] bpf, doc: rename txt files to rst files

This will cause them to get auto rendered, e.g. when viewing them on GitHub. Followup patches will correct the content to be RST compliant. Also adjust README.rst to point to the renamed files. Signed-off-by: Jesper Dangaard Brouer --- Documentation/bpf/README.rst|

[bpf-next PATCH 1/5] bpf, doc: add basic README.rst file

A README.rst file in a directory have special meaning for sites like github, which auto renders the contents. Plus search engines like Google also index these README.rst files. Auto rendering allow us to use links, for (re)directing eBPF users to other places where docs live. The end-goal would

[bpf-next PATCH 0/5] bpf, doc: convert Documentation/bpf to RST-formatting

The kernel is moving files under Documentation to use the RST (reStructuredText) format and Sphinx [1]. This patchset converts the files under Documentation/bpf/ into RST format. The Sphinx integration is left as followup work. [1] https://www.kernel.org/doc/html/latest/doc-guide/sphinx.html

Re: [RFC PATCH 1/2] scripts/kernel-doc: Auto-detect common code-blocks

On Thu, 10 May 2018, Jonathan Corbet wrote: > On Thu, 10 May 2018 09:34:56 -0700 > Matthew Wilcox wrote: > >> I think this is a bit fragile. Why not just search for ':\n'? Is >> there ever a case where we want to write: >> >> /** >> * foo is a bar: >> *

Re: [RFC PATCH v3 0/6] Documentation/features: Provide and apply 'features-refresh.sh'

* Jonathan Corbet wrote: > On Mon, 7 May 2018 12:43:37 +0200 > Andrea Parri wrote: > > > This series provides the script 'features-refresh.sh', which operates on > > the arch support status files, and it applies this script to refresh the >

[PATCH 0/3] docs/vm: transhuge: split userspace bits to admin-guide/mm

Hi, Here are minor updates to transparent hugepage docs. Except from minor formatting and spelling updates, these patches re-arrange the transhuge.rst so that userspace interface description will not be interleaved with the implementation details and it would be possible to split the userspace

[PATCH 1/3] docs/vm: transhuge: change sections order

so that userspace interface and implementation description will be grouped together Signed-off-by: Mike Rapoport --- Documentation/vm/transhuge.rst | 82 +- 1 file changed, 41 insertions(+), 41 deletions(-) diff --git

[PATCH 2/3] docs/vm: transhuge: minor updates

Some formatting changes and addition of a sentence introducing khugepaged Signed-off-by: Mike Rapoport --- Documentation/vm/transhuge.rst | 47 -- 1 file changed, 36 insertions(+), 11 deletions(-) diff --git

[tip:timers/core] timers: Adjust a kernel-doc comment

Commit-ID: bf9c96bec76fbc4424b4c70be563af4107d8044f Gitweb: https://git.kernel.org/tip/bf9c96bec76fbc4424b4c70be563af4107d8044f Author: Mauro Carvalho Chehab AuthorDate: Mon, 7 May 2018 06:35:48 -0300 Committer: Thomas Gleixner

Re: [PATCH] PM: docs: sleep-states: Fix a typo ("includig")

On Wednesday, April 25, 2018 12:07:03 PM CEST Jonathan Neuschäfer wrote: > Signed-off-by: Jonathan Neuschäfer > --- > Documentation/admin-guide/pm/sleep-states.rst | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git

Re: [PATCH] Documentation/admin-guide/pm/intel_pstate: fix Active Mode w/o HWP paragraph

On Tuesday, May 8, 2018 8:36:44 PM CEST Srinivas Pandruvada wrote: > On Tue, 2018-05-08 at 17:12 +0200, Juri Lelli wrote: > > P-state selection algorithm (powersave or performance) is selected by > > echoing the desired choice to scaling_governor sysfs attribute and > > not > > to scaling_cur_freq

[PATCH v3 1/3] Documentation: ioctl-number: add ddbridge IOCTLs

From: Daniel Scheller drivers/media/pci/ddbridge exposes a few IOCTLs which are used by userspace utilities to ie. update PCIe card's FPGA firmware. The IOCTLs chosen are in the range 0xDD/0xE0 up to 0xDD/0xFF, with 0xDD as sort of gimmick for "Digital Devices". To not

Re: [PATCH 4/6] mm, arm64: untag user addresses in mm/gup.c

On Tue, May 8, 2018 at 5:11 PM, Catalin Marinas wrote: > On Wed, May 02, 2018 at 07:25:17PM +0200, Andrey Konovalov wrote: >> On Wed, May 2, 2018 at 5:36 PM, Kirill A. Shutemov >> wrote: >> > On Wed, May 02, 2018 at 02:38:42PM +,

Re: [PATCH v5 5/7] ocxl: Expose the thread_id needed for wait on POWER9

Le 11/05/2018 à 12:06, Alastair D'Silva a écrit : -Original Message- From: Frederic Barrat Sent: Friday, 11 May 2018 7:25 PM To: Alastair D'Silva ; linuxppc-...@lists.ozlabs.org Cc: linux-ker...@vger.kernel.org; linux-doc@vger.kernel.org;

RE: [PATCH v5 5/7] ocxl: Expose the thread_id needed for wait on POWER9

> -Original Message- > From: Frederic Barrat > Sent: Friday, 11 May 2018 7:25 PM > To: Alastair D'Silva ; linuxppc-...@lists.ozlabs.org > Cc: linux-ker...@vger.kernel.org; linux-doc@vger.kernel.org; > mi...@neuling.org;

Re: [PATCH v5 7/7] ocxl: Document new OCXL IOCTLs

Le 11/05/2018 à 08:13, Alastair D'Silva a écrit : From: Alastair D'Silva Signed-off-by: Alastair D'Silva --- Acked-by: Frederic Barrat Documentation/accelerators/ocxl.rst | 11 +++ 1 file changed, 11

Re: [PATCH v5 6/7] ocxl: Add an IOCTL so userspace knows what OCXL features are available

Le 11/05/2018 à 08:13, Alastair D'Silva a écrit : From: Alastair D'Silva In order for a userspace AFU driver to call the POWER9 specific OCXL_IOCTL_ENABLE_P9_WAIT, it needs to verify that it can actually make that call. Signed-off-by: Alastair D'Silva

Re: [PATCH v5 5/7] ocxl: Expose the thread_id needed for wait on POWER9

Le 11/05/2018 à 08:13, Alastair D'Silva a écrit : From: Alastair D'Silva In order to successfully issue as_notify, an AFU needs to know the TID to notify, which in turn means that this information should be available in userspace so it can be communicated to the AFU.

Re: [PATCH v5 3/7] powerpc: use task_pid_nr() for TID allocation

Le 11/05/2018 à 08:12, Alastair D'Silva a écrit : From: Alastair D'Silva The current implementation of TID allocation, using a global IDR, may result in an errant process starving the system of available TIDs. Instead, use task_pid_nr(), as mentioned by the original

Re: [PATCH v5 4/7] ocxl: Rename pnv_ocxl_spa_remove_pe to clarify it's action

Le 11/05/2018 à 08:13, Alastair D'Silva a écrit : From: Alastair D'Silva The function removes the process element from NPU cache. Signed-off-by: Alastair D'Silva --- Acked-by: Frederic Barrat

Re: [PATCH v5 2/7] powerpc: Use TIDR CPU feature to control TIDR allocation

Le 11/05/2018 à 08:12, Alastair D'Silva a écrit : From: Alastair D'Silva Switch the use of TIDR on it's CPU feature, rather than assuming it is available based on architecture. Signed-off-by: Alastair D'Silva --- Reviewed-by: Frederic Barrat

Re: [PATCH v5 1/7] powerpc: Add TIDR CPU feature for POWER9

Le 11/05/2018 à 08:12, Alastair D'Silva a écrit : From: Alastair D'Silva This patch adds a CPU feature bit to show whether the CPU has the TIDR register available, enabling as_notify/wait in userspace. Signed-off-by: Alastair D'Silva ---

Re: [PATCH 13/18] wait: wait.h: Get rid of a kernel-doc/Sphinx warnings

> Am 10.05.2018 um 18:42 schrieb Mauro Carvalho Chehab > : > > Em Thu, 10 May 2018 09:38:46 -0600 > Jonathan Corbet escreveu: > >> On Thu, 10 May 2018 11:21:13 -0300 >> Mauro Carvalho Chehab wrote: >> >>> The problem

[PATCH v5 5/7] ocxl: Expose the thread_id needed for wait on POWER9

From: Alastair D'Silva In order to successfully issue as_notify, an AFU needs to know the TID to notify, which in turn means that this information should be available in userspace so it can be communicated to the AFU. Signed-off-by: Alastair D'Silva

[PATCH v5 7/7] ocxl: Document new OCXL IOCTLs

From: Alastair D'Silva Signed-off-by: Alastair D'Silva --- Documentation/accelerators/ocxl.rst | 11 +++ 1 file changed, 11 insertions(+) diff --git a/Documentation/accelerators/ocxl.rst b/Documentation/accelerators/ocxl.rst index

[PATCH v5 4/7] ocxl: Rename pnv_ocxl_spa_remove_pe to clarify it's action

From: Alastair D'Silva The function removes the process element from NPU cache. Signed-off-by: Alastair D'Silva --- arch/powerpc/include/asm/pnv-ocxl.h | 2 +- arch/powerpc/platforms/powernv/ocxl.c | 4 ++-- drivers/misc/ocxl/link.c |

[PATCH v5 3/7] powerpc: use task_pid_nr() for TID allocation

From: Alastair D'Silva The current implementation of TID allocation, using a global IDR, may result in an errant process starving the system of available TIDs. Instead, use task_pid_nr(), as mentioned by the original author. The scenario described which prevented it's use

[PATCH v5 1/7] powerpc: Add TIDR CPU feature for POWER9

From: Alastair D'Silva This patch adds a CPU feature bit to show whether the CPU has the TIDR register available, enabling as_notify/wait in userspace. Signed-off-by: Alastair D'Silva --- arch/powerpc/include/asm/cputable.h | 3 ++-

[PATCH v5 0/7] ocxl: Implement Power9 as_notify/wait for OpenCAPI

From: Alastair D'Silva The Power 9 as_notify/wait feature provides a lower latency way to signal a thread that work is complete. This series enables the use of this feature from OpenCAPI adapters, as well as addressing a potential starvation issue when allocating thread

[PATCH v5 6/7] ocxl: Add an IOCTL so userspace knows what OCXL features are available

From: Alastair D'Silva In order for a userspace AFU driver to call the POWER9 specific OCXL_IOCTL_ENABLE_P9_WAIT, it needs to verify that it can actually make that call. Signed-off-by: Alastair D'Silva --- drivers/misc/ocxl/file.c | 25

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