[PATCH v1 8/9] drm/doc: Add initial komeda driver documentation
Signed-off-by: James (Qian) Wang --- Documentation/gpu/drivers.rst| 1 + Documentation/gpu/komeda-kms.rst | 483 +++ 2 files changed, 484 insertions(+) create mode 100644 Documentation/gpu/komeda-kms.rst diff --git a/Documentation/gpu/drivers.rst b/Documentation/gpu/drivers.rst index 7c1672118a73..978e6da9bbff 100644 --- a/Documentation/gpu/drivers.rst +++ b/Documentation/gpu/drivers.rst @@ -17,6 +17,7 @@ GPU Driver Documentation vkms bridge/dw-hdmi xen-front + komeda-kms .. only:: subproject and html diff --git a/Documentation/gpu/komeda-kms.rst b/Documentation/gpu/komeda-kms.rst new file mode 100644 index ..8af925ca0869 --- /dev/null +++ b/Documentation/gpu/komeda-kms.rst @@ -0,0 +1,483 @@ +.. SPDX-License-Identifier: GPL-2.0 + +== + drm/komeda ARM display driver +== + +The drm/komeda driver supports for the ARM display processor D71 and later +IPs, this document is for giving a brief overview of driver design: how it +works and why design it like that. + +Overview of D71 like display IPs + + +From D71, Arm display IP begins to adopt a flexible and modularized +architecture. A display pipeline is made up of multiple individual and +functional pipeline stages called components, and every component has some +specific capabilities that can give the flowed pipeline pixel data a +particular processing. + +Typical D71 components: + +Layer +- +Layer is the first pipeline stage, which is for preparing the pixel data +for the next stage. It fetches the pixel from memory, decodes it if it's +AFBC, rotates the source image, unpacks or converts YUV pixels to the device +internal RGB pixels, then adjust the color_space of pixels if need. + +Scaler +-- +As its name, scaler is taking responsability for scaling, and D71 also +supports image enhancements by scaler. +The usage of scaler is very flexible and can be connected to layer output +for layer scaling, or connected to compositor and scale the whole display +frame and then feed the output data into wb_layer which will then write it +into memory. + +Compositor (compiz) +--- +Compositor is for blending multiple layers or pixel data flows into one +single display frame, and its output frame can be fed into post image +processor and then on the monitor or fed into wb_layer and written to memory +at the same time. And user also can insert a scaler between compositor and +wb_layer to down scale the display frame first and then writing to memory. + +Writeback Layer (wb_layer) +-- +Writeback layer do the opposite things of Layer, Which connect to compiz and try +to write the composition result to memory. + +Post image processor (improc) +- +Post image processor is for adjusting frame data like gamma and color space +to fit the requirements of the monitor. + +Timing controller (timing_ctrlr) + +Final stage of display pipeline, Timing controller is not for the pixel +handling, but only for controlling the display timing. + +Merger +-- +D71 scaler mostly only has half the horizontal input/output capabilities compare +with Layer, Like if Layer supports 4K input size, the scaler only can supports +2K input/output in some time. To achieve the fully frame scaling, D71 introduce +Layer Split, which split the whole image to two half part and feed them to two +Layers A and B, and do the scaling independently, after scaling the result need +to be feed to merger to merge two part image, and then output to compiz. + +Splitter + +Similar to Layer Split, but Splitter is used for writeback, which split the +compiz result to two part and then feed them to two scaler. + +Possible D71 Pipeline usage +=== + +Benefit from the modularized architecture, D71 pipelines can be easily adjusted +to fit different usages, following are some typical pipeline data flow +configurations: + +Single pipeline data flow +- + +.. kernel-render:: DOT + :alt: Single pipeline digraph + :caption: Single pipeline data flow + + digraph single_ppl { + rankdir=LR; + + subgraph { + "Memory"; + "Monitor"; + } + + subgraph cluster_pipeline { + style=dashed + node [shape=box] + { + node [bgcolor=grey style=dashed] + "Scaler-0"; + "Scaler-1"; + "Scaler-0/1" + } + + node [bgcolor=grey style=filled] + "Layer-0" -> "Scaler-0" + "Layer-1" -> "Scaler-0" + "Layer-2" -> "Scaler-1" + "Layer-3" -> "Scaler-1" + + "Layer-0" -> "Compiz" + "Layer-1" -> "Compiz" + "Layer-2" -> "Compiz" + "Layer-3" -> "Compiz" + "Scaler-0" -> "Compiz" + "Scaler-1" -> "Compiz" + + "Compiz" -> "Scaler-0/1" ->
[PATCH v1 8/9] drm/doc: Add initial komeda driver documentation
Signed-off-by: James (Qian) Wang --- Documentation/gpu/drivers.rst| 1 + Documentation/gpu/komeda-kms.rst | 483 +++ 2 files changed, 484 insertions(+) create mode 100644 Documentation/gpu/komeda-kms.rst diff --git a/Documentation/gpu/drivers.rst b/Documentation/gpu/drivers.rst index 7c1672118a73..978e6da9bbff 100644 --- a/Documentation/gpu/drivers.rst +++ b/Documentation/gpu/drivers.rst @@ -17,6 +17,7 @@ GPU Driver Documentation vkms bridge/dw-hdmi xen-front + komeda-kms .. only:: subproject and html diff --git a/Documentation/gpu/komeda-kms.rst b/Documentation/gpu/komeda-kms.rst new file mode 100644 index ..8af925ca0869 --- /dev/null +++ b/Documentation/gpu/komeda-kms.rst @@ -0,0 +1,483 @@ +.. SPDX-License-Identifier: GPL-2.0 + +== + drm/komeda ARM display driver +== + +The drm/komeda driver supports for the ARM display processor D71 and later +IPs, this document is for giving a brief overview of driver design: how it +works and why design it like that. + +Overview of D71 like display IPs + + +From D71, Arm display IP begins to adopt a flexible and modularized +architecture. A display pipeline is made up of multiple individual and +functional pipeline stages called components, and every component has some +specific capabilities that can give the flowed pipeline pixel data a +particular processing. + +Typical D71 components: + +Layer +- +Layer is the first pipeline stage, which is for preparing the pixel data +for the next stage. It fetches the pixel from memory, decodes it if it's +AFBC, rotates the source image, unpacks or converts YUV pixels to the device +internal RGB pixels, then adjust the color_space of pixels if need. + +Scaler +-- +As its name, scaler is taking responsability for scaling, and D71 also +supports image enhancements by scaler. +The usage of scaler is very flexible and can be connected to layer output +for layer scaling, or connected to compositor and scale the whole display +frame and then feed the output data into wb_layer which will then write it +into memory. + +Compositor (compiz) +--- +Compositor is for blending multiple layers or pixel data flows into one +single display frame, and its output frame can be fed into post image +processor and then on the monitor or fed into wb_layer and written to memory +at the same time. And user also can insert a scaler between compositor and +wb_layer to down scale the display frame first and then writing to memory. + +Writeback Layer (wb_layer) +-- +Writeback layer do the opposite things of Layer, Which connect to compiz and try +to write the composition result to memory. + +Post image processor (improc) +- +Post image processor is for adjusting frame data like gamma and color space +to fit the requirements of the monitor. + +Timing controller (timing_ctrlr) + +Final stage of display pipeline, Timing controller is not for the pixel +handling, but only for controlling the display timing. + +Merger +-- +D71 scaler mostly only has half the horizontal input/output capabilities compare +with Layer, Like if Layer supports 4K input size, the scaler only can supports +2K input/output in some time. To achieve the fully frame scaling, D71 introduce +Layer Split, which split the whole image to two half part and feed them to two +Layers A and B, and do the scaling independently, after scaling the result need +to be feed to merger to merge two part image, and then output to compiz. + +Splitter + +Similar to Layer Split, but Splitter is used for writeback, which split the +compiz result to two part and then feed them to two scaler. + +Possible D71 Pipeline usage +=== + +Benefit from the modularized architecture, D71 pipelines can be easily adjusted +to fit different usages, following are some typical pipeline data flow +configurations: + +Single pipeline data flow +- + +.. kernel-render:: DOT + :alt: Single pipeline digraph + :caption: Single pipeline data flow + + digraph single_ppl { + rankdir=LR; + + subgraph { + "Memory"; + "Monitor"; + } + + subgraph cluster_pipeline { + style=dashed + node [shape=box] + { + node [bgcolor=grey style=dashed] + "Scaler-0"; + "Scaler-1"; + "Scaler-0/1" + } + + node [bgcolor=grey style=filled] + "Layer-0" -> "Scaler-0" + "Layer-1" -> "Scaler-0" + "Layer-2" -> "Scaler-1" + "Layer-3" -> "Scaler-1" + + "Layer-0" -> "Compiz" + "Layer-1" -> "Compiz" + "Layer-2" -> "Compiz" + "Layer-3" -> "Compiz" + "Scaler-0" -> "Compiz" + "Scaler-1" -> "Compiz" + + "Compiz" -> "Scaler-0/1" ->