Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

On Mon, May 21, 2018 at 4:10 PM, Mark Rutland wrote: > On Mon, May 21, 2018 at 11:37:12AM +0100, Mark Rutland wrote: >> Hi Ganapat, >> >> >> Sorry for the delay in replying; I was away most of last week. >> >> On Tue, May 15, 2018 at 04:03:19PM +0530, Ganapatrao Kulkarni

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

Hi Mark, On Mon, May 21, 2018 at 4:25 PM, Mark Rutland wrote: > On Sat, May 05, 2018 at 12:16:13AM +0530, Ganapatrao Kulkarni wrote: >> On Thu, Apr 26, 2018 at 4:29 PM, Mark Rutland wrote: >> > On Wed, Apr 25, 2018 at 02:30:47PM +0530, Ganapatrao

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

On Sat, May 05, 2018 at 12:16:13AM +0530, Ganapatrao Kulkarni wrote: > On Thu, Apr 26, 2018 at 4:29 PM, Mark Rutland wrote: > > On Wed, Apr 25, 2018 at 02:30:47PM +0530, Ganapatrao Kulkarni wrote: > >> + * > >> + * L3 Tile and DMC channel selection is through SMC call > >>

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

On Mon, May 21, 2018 at 11:37:12AM +0100, Mark Rutland wrote: > Hi Ganapat, > > > Sorry for the delay in replying; I was away most of last week. > > On Tue, May 15, 2018 at 04:03:19PM +0530, Ganapatrao Kulkarni wrote: > > On Sat, May 5, 2018 at 12:16 AM, Ganapatrao Kulkarni

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

Hi Ganapat, Sorry for the delay in replying; I was away most of last week. On Tue, May 15, 2018 at 04:03:19PM +0530, Ganapatrao Kulkarni wrote: > On Sat, May 5, 2018 at 12:16 AM, Ganapatrao Kulkarni > wrote: > > On Thu, Apr 26, 2018 at 4:29 PM, Mark Rutland

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

Hi Mark, On Sat, May 5, 2018 at 12:16 AM, Ganapatrao Kulkarni wrote: > Hi Mark, > > On Thu, Apr 26, 2018 at 4:29 PM, Mark Rutland wrote: >> Hi, >> >> On Wed, Apr 25, 2018 at 02:30:47PM +0530, Ganapatrao Kulkarni wrote: >>> + >>> +/* L3c and DMC has 16

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

On Fri, 4 May 2018 18:10:44 +0100 Robin Murphy wrote: > Hi Kim, Hi Robin, > On 04/05/18 01:30, Kim Phillips wrote: > > On Tue, 1 May 2018 12:54:05 +0100 > > Will Deacon wrote: > >> On Fri, Apr 27, 2018 at 11:56:25AM -0500, Kim Phillips wrote: > >>>

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

Hi Mark, On Thu, Apr 26, 2018 at 4:29 PM, Mark Rutland wrote: > Hi, > > On Wed, Apr 25, 2018 at 02:30:47PM +0530, Ganapatrao Kulkarni wrote: >> + >> +/* L3c and DMC has 16 and 8 channels per socket respectively. >> + * Each Channel supports UNCORE PMU device and consists of

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

Hi Kim, On 04/05/18 01:30, Kim Phillips wrote: On Tue, 1 May 2018 12:54:05 +0100 Will Deacon wrote: Hi Kim, Hi Will, thanks for responding. On Fri, Apr 27, 2018 at 11:56:25AM -0500, Kim Phillips wrote: On Fri, 27 Apr 2018 17:09:14 +0100 Will Deacon

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

On Tue, 1 May 2018 12:54:05 +0100 Will Deacon wrote: > Hi Kim, Hi Will, thanks for responding. > On Fri, Apr 27, 2018 at 11:56:25AM -0500, Kim Phillips wrote: > > On Fri, 27 Apr 2018 17:09:14 +0100 > > Will Deacon wrote: > > > On Fri, Apr 27, 2018 at

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

Hi Kim, On Fri, Apr 27, 2018 at 11:56:25AM -0500, Kim Phillips wrote: > On Fri, 27 Apr 2018 17:09:14 +0100 > Will Deacon wrote: > > On Fri, Apr 27, 2018 at 10:46:29AM -0500, Kim Phillips wrote: > > > On Fri, 27 Apr 2018 15:37:20 +0100 > > > Will Deacon

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

On Fri, 27 Apr 2018 17:09:14 +0100 Will Deacon wrote: > Kim, > > [Ganapat: please don't let this discussion disrupt your PMU driver > development. You can safely ignore it for now :)] > > On Fri, Apr 27, 2018 at 10:46:29AM -0500, Kim Phillips wrote: > > On Fri, 27 Apr

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

Kim, [Ganapat: please don't let this discussion disrupt your PMU driver development. You can safely ignore it for now :)] On Fri, Apr 27, 2018 at 10:46:29AM -0500, Kim Phillips wrote: > On Fri, 27 Apr 2018 15:37:20 +0100 > Will Deacon wrote: > > > On Fri, Apr 27, 2018 at

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

On Fri, 27 Apr 2018 15:37:20 +0100 Will Deacon wrote: > On Fri, Apr 27, 2018 at 08:15:25AM -0500, Kim Phillips wrote: > > On Fri, 27 Apr 2018 10:30:27 +0100 > > Mark Rutland wrote: > > > On Thu, Apr 26, 2018 at 05:06:24PM -0500, Kim Phillips wrote: > >

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

On Fri, Apr 27, 2018 at 08:15:25AM -0500, Kim Phillips wrote: > On Fri, 27 Apr 2018 10:30:27 +0100 > Mark Rutland wrote: > > On Thu, Apr 26, 2018 at 05:06:24PM -0500, Kim Phillips wrote: > > > On Wed, 25 Apr 2018 14:30:47 +0530 > > > Ganapatrao Kulkarni

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

On Fri, 27 Apr 2018 10:30:27 +0100 Mark Rutland wrote: > Hi Kim, > > On Thu, Apr 26, 2018 at 05:06:24PM -0500, Kim Phillips wrote: > > On Wed, 25 Apr 2018 14:30:47 +0530 > > Ganapatrao Kulkarni wrote: > > > > > +static int

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

Hi Kim, On Thu, Apr 26, 2018 at 05:06:24PM -0500, Kim Phillips wrote: > On Wed, 25 Apr 2018 14:30:47 +0530 > Ganapatrao Kulkarni wrote: > > > +static int thunderx2_uncore_event_init(struct perf_event *event) > This PMU driver can be made more user-friendly by

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

On Wed, 25 Apr 2018 14:30:47 +0530 Ganapatrao Kulkarni wrote: > +static int thunderx2_uncore_event_init(struct perf_event *event) ... > + /* > + * SOC PMU counters are shared across all cores. > + * Therefore, it does not support per-process mode. >

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

Hi, On Wed, Apr 25, 2018 at 02:30:47PM +0530, Ganapatrao Kulkarni wrote: > + > +/* L3c and DMC has 16 and 8 channels per socket respectively. > + * Each Channel supports UNCORE PMU device and consists of > + * 4 independent programmable counters. Counters are 32 bit > + * and does not support

[PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory Controller(DMC) and Level 3 Cache(L3C). ThunderX2 has 8 independent DMC PMUs to capture performance events corresponding to 8 channels of DDR4 Memory Controller and 16 independent L3C PMUs to capture events corresponding to 16