Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

2017-02-07 Thread Christopher Covington
On 02/01/2017 01:38 PM, Catalin Marinas wrote: > On Wed, Feb 01, 2017 at 06:34:01PM +, Will Deacon wrote: >> On Wed, Feb 01, 2017 at 06:22:44PM +, Catalin Marinas wrote: >>> On Wed, Feb 01, 2017 at 05:59:48PM +, Will Deacon wrote: On Wed, Feb 01, 2017 at 05:49:34PM +, Catalin

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

2017-02-01 Thread Catalin Marinas
On Wed, Feb 01, 2017 at 06:34:01PM +, Will Deacon wrote: > On Wed, Feb 01, 2017 at 06:22:44PM +, Catalin Marinas wrote: > > On Wed, Feb 01, 2017 at 05:59:48PM +, Will Deacon wrote: > > > On Wed, Feb 01, 2017 at 05:49:34PM +, Catalin Marinas wrote: > > > > On Wed, Feb 01, 2017 at

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

2017-02-01 Thread Will Deacon
On Wed, Feb 01, 2017 at 06:22:44PM +, Catalin Marinas wrote: > On Wed, Feb 01, 2017 at 05:59:48PM +, Will Deacon wrote: > > On Wed, Feb 01, 2017 at 05:49:34PM +, Catalin Marinas wrote: > > > On Wed, Feb 01, 2017 at 05:41:05PM +, Will Deacon wrote: > > > > Maybe > > > > just select

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

2017-02-01 Thread Catalin Marinas
On Wed, Feb 01, 2017 at 05:59:48PM +, Will Deacon wrote: > On Wed, Feb 01, 2017 at 05:49:34PM +, Catalin Marinas wrote: > > On Wed, Feb 01, 2017 at 05:41:05PM +, Will Deacon wrote: > > > On Wed, Feb 01, 2017 at 05:36:09PM +, Catalin Marinas wrote: > > > > On Wed, Feb 01, 2017 at

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

2017-02-01 Thread Will Deacon
On Wed, Feb 01, 2017 at 05:49:34PM +, Catalin Marinas wrote: > On Wed, Feb 01, 2017 at 05:41:05PM +, Will Deacon wrote: > > On Wed, Feb 01, 2017 at 05:36:09PM +, Catalin Marinas wrote: > > > On Wed, Feb 01, 2017 at 04:33:58PM +, Will Deacon wrote: > > > > On Wed, Feb 01, 2017 at

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

2017-02-01 Thread Catalin Marinas
On Wed, Feb 01, 2017 at 05:49:34PM +, Catalin Marinas wrote: > On Wed, Feb 01, 2017 at 05:41:05PM +, Will Deacon wrote: > > On Wed, Feb 01, 2017 at 05:36:09PM +, Catalin Marinas wrote: > > > On Wed, Feb 01, 2017 at 04:33:58PM +, Will Deacon wrote: > > > > On Wed, Feb 01, 2017 at

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

2017-02-01 Thread Catalin Marinas
On Wed, Feb 01, 2017 at 05:41:05PM +, Will Deacon wrote: > On Wed, Feb 01, 2017 at 05:36:09PM +, Catalin Marinas wrote: > > On Wed, Feb 01, 2017 at 04:33:58PM +, Will Deacon wrote: > > > On Wed, Feb 01, 2017 at 11:29:22AM -0500, Christopher Covington wrote: > > > > On 01/31/2017 12:56

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

2017-02-01 Thread Will Deacon
On Wed, Feb 01, 2017 at 05:36:09PM +, Catalin Marinas wrote: > On Wed, Feb 01, 2017 at 04:33:58PM +, Will Deacon wrote: > > On Wed, Feb 01, 2017 at 11:29:22AM -0500, Christopher Covington wrote: > > > On 01/31/2017 12:56 PM, Marc Zyngier wrote: > > > > Given that all ARMv8 CPUs can support

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

2017-02-01 Thread Catalin Marinas
On Wed, Feb 01, 2017 at 04:33:58PM +, Will Deacon wrote: > On Wed, Feb 01, 2017 at 11:29:22AM -0500, Christopher Covington wrote: > > On 01/31/2017 12:56 PM, Marc Zyngier wrote: > > > Given that all ARMv8 CPUs can support SW_PAN, it is more likely to be > > > enabled than the ARMv8.1 PAN. I'd

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

2017-02-01 Thread Christopher Covington
On 01/31/2017 12:56 PM, Marc Zyngier wrote: > On 31/01/17 17:48, Christopher Covington wrote: >> On 01/31/2017 07:37 AM, Mark Rutland wrote: >>> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

2017-01-31 Thread Marc Zyngier
On 31/01/17 17:48, Christopher Covington wrote: > On 01/31/2017 07:37 AM, Mark Rutland wrote: >> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: >>> The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries >>> using an incorrect ASID when TTBRx_EL1 is

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

2017-01-31 Thread Christopher Covington
On 01/31/2017 07:37 AM, Mark Rutland wrote: > On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: >> The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries >> using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum >> is triggered, page

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

2017-01-31 Thread Mark Rutland
On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: > The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries > using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum > is triggered, page table entries using the new translation table base >

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

2017-01-30 Thread Christopher Covington
Hi Mark, On 01/30/2017 05:56 AM, Mark Rutland wrote: > Hi, > > On Fri, Jan 27, 2017 at 04:52:23PM -0500, Christopher Covington wrote: >> On 01/27/2017 09:38 AM, Mark Rutland wrote: >>> On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: > Replacing the above sequence

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

2017-01-27 Thread Christopher Covington
Hi Mark, On 01/27/2017 09:38 AM, Mark Rutland wrote: > On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: >> The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries >> using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum >> is

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

2017-01-27 Thread Timur Tabi
On 01/25/2017 09:52 AM, Christopher Covington wrote: + .desc = "Qualcomm Falkor erratum 1003", FYI, this needs to say, "Qualcomm Technologies Falkor ...". Same thing with the 1009 patch. -- Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

2017-01-27 Thread Mark Rutland
On Wed, Jan 25, 2017 at 10:52:30AM -0500, Christopher Covington wrote: > The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries > using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum > is triggered, page table entries using the new translation table base >