Re: [PATCH v4 5/6] arm64: dts: sdm845: Add serial console support

2018-03-21 Thread Rajendra Nayak 


On 3/21/2018 1:09 AM, Stephen Boyd wrote:

Quoting Karthikeyan Ramasubramanian (2018-03-14 16:58:50)

diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts 
b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index 979ab49..ea3efc5 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -12,4 +12,43 @@
  / {
 model = "Qualcomm Technologies, Inc. SDM845 MTP";
 compatible = "qcom,sdm845-mtp";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0";


Also add :115200n8 ?



+   };
+};
+
+ {


I think the method is to put these inside soc node without using the
phandle reference. So indent everything once more.


Some of this was discussed in the previous versions [1] and we arrived
at a consensus to follow this way of doing it.
Bjorn also said he was going to do a series to move all the existing
dts files to follow similar convention so its all consistent.

https://lkml.org/lkml/2018/2/6/676




+   geniqup@ac {
+   serial@a84000 {
+   status = "okay";
+   };
+   };
+
+   pinctrl@340 {
+   qup-uart2-default {
+   pinconf_tx {
+   pins = "gpio4";
+   drive-strength = <2>;
+   bias-disable;
+   };
+
+   pinconf_rx {
+   pins = "gpio5";
+   drive-strength = <2>;
+   bias-pull-up;
+   };
+   };
+
+   qup-uart2-sleep {
+   pinconf {
+   pins = "gpio4", "gpio5";
+   bias-pull-down;
+   };
+   };
+   };
  };
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi 
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 32f8561..59334d9 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -6,6 +6,7 @@
   */
  
  #include 

+#include 
  
  / {

 interrupt-parent = <>;
@@ -194,6 +195,20 @@
 #gpio-cells = <2>;
 interrupt-controller;
 #interrupt-cells = <2>;
+
+   qup_uart2_default: qup-uart2-default {
+   pinmux {
+   function = "qup9";
+   pins = "gpio4", "gpio5";
+   };
+   };
+
+   qup_uart2_sleep: qup-uart2-sleep {
+   pinmux {
+   function = "gpio";
+   pins = "gpio4", "gpio5";
+   };
+   };


Are these supposed to go to the board file?


Again, this was discussed in the previous versions, and we decided it
makes sense to have the pinmux (default) which rarely changes across
boards in the SoC file, and have boards specify the pinconf (electrical)
properties.
And get rid of all the soc-pins/board-pins/pmic-pins files.

https://lkml.org/lkml/2018/2/6/693

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Re: [PATCH v4 5/6] arm64: dts: sdm845: Add serial console support

2018-03-20 Thread Stephen Boyd 
Quoting Karthikeyan Ramasubramanian (2018-03-14 16:58:50)
> diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts 
> b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
> index 979ab49..ea3efc5 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
> +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
> @@ -12,4 +12,43 @@
>  / {
> model = "Qualcomm Technologies, Inc. SDM845 MTP";
> compatible = "qcom,sdm845-mtp";
> +
> +   aliases {
> +   serial0 = 
> +   };
> +
> +   chosen {
> +   stdout-path = "serial0";

Also add :115200n8 ?


> +   };
> +};
> +
> + {

I think the method is to put these inside soc node without using the
phandle reference. So indent everything once more.

> +   geniqup@ac {
> +   serial@a84000 {
> +   status = "okay";
> +   };
> +   };
> +
> +   pinctrl@340 {
> +   qup-uart2-default {
> +   pinconf_tx {
> +   pins = "gpio4";
> +   drive-strength = <2>;
> +   bias-disable;
> +   };
> +
> +   pinconf_rx {
> +   pins = "gpio5";
> +   drive-strength = <2>;
> +   bias-pull-up;
> +   };
> +   };
> +
> +   qup-uart2-sleep {
> +   pinconf {
> +   pins = "gpio4", "gpio5";
> +   bias-pull-down;
> +   };
> +   };
> +   };
>  };
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi 
> b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 32f8561..59334d9 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -6,6 +6,7 @@
>   */
>  
>  #include 
> +#include 
>  
>  / {
> interrupt-parent = <>;
> @@ -194,6 +195,20 @@
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> +
> +   qup_uart2_default: qup-uart2-default {
> +   pinmux {
> +   function = "qup9";
> +   pins = "gpio4", "gpio5";
> +   };
> +   };
> +
> +   qup_uart2_sleep: qup-uart2-sleep {
> +   pinmux {
> +   function = "gpio";
> +   pins = "gpio4", "gpio5";
> +   };
> +   };

Are these supposed to go to the board file?

> };
>  
> timer@17c9 {
> @@ -272,5 +287,28 @@
> #interrupt-cells = <4>;
> cell-index = <0>;
> };
> +
> +   geniqup@ac {
> +   compatible = "qcom,geni-se-qup";
> +   reg = <0xac 0x6000>;
> +   clock-names = "m-ahb", "s-ahb";
> +   clocks = < GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> +< GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> +   #address-cells = <1>;
> +   #size-cells = <1>;
> +   ranges;

Add a status = "disabled" here too.

> +
> +   uart2: serial@a84000 {
> +   compatible = "qcom,geni-debug-uart";
> +   reg = <0xa84000 0x4000>;
> +   clock-names = "se";
> +   clocks = < GCC_QUPV3_WRAP1_S1_CLK>;
> +   pinctrl-names = "default", "sleep";
> +   pinctrl-0 = <_uart2_default>;
> +   pinctrl-1 = <_uart2_sleep>;
> +   interrupts =  IRQ_TYPE_LEVEL_HIGH>;
> +   status = "disabled";
> +   };
> +   };
> };
>  };
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