Add bindings documentation for Altera SOCFPGA bridges:
* fpga2sdram
* fpga2hps
* hps2fpga
* lwhps2fpga
Signed-off-by: Alan Tull <at...@opensource.altera.com>
Signed-off-by: Matthew Gerlach <mgerl...@altera.com>
Signed-off-by: Dinh Nguyen <dingu...@opensource.altera.com>
* fpga_bridges_put
Signed-off-by: Alan Tull <at...@opensource.altera.com>
---
v2: Minor cleanup
v12: Bump version to line up with simple fpga bus
Remove sysfs
Improve get/put functions, get the low level driver too.
Clean up class implementation
Add kernel doc documentation
FPGA Regions support programming FPGA under control of the Device
Tree.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
---
v9: initial version (this patch added during rest of patchset's v9)
v10: request deferral if fpga mgr or bridges not available yet
cleanup as fpga manage
during probe. If the property
does not exist, the driver will leave the bridge in its
current state.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
Signed-off-by: Matthew Gerlach <mgerl...@altera.com>
Signed-off-by: Dinh Nguyen <dingu...@opensource.altera.com>
---
v2:
Add low level driver to support reprogramming FPGAs for Altera
SoCFPGA Arria10.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
---
v19: Added to this patchset as has been changed to use
fpga image information struct
a checkpatch fix of a block comment
do not use c
Add documentation for new FPGA bridge class's sysfs interface.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
Acked-by: Moritz Fischer <moritz.fisc...@ettus.com>
--
v15: Document added in v15 of patch set
v16: No change to this patch in v16 of patch set
v17: No change to this
New bindings document for FPGA Region to support programming
FPGA's under Device Tree control
Signed-off-by: Alan Tull <at...@opensource.altera.com>
Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
v9: initial version adde
Add documentation for new FPGA bridge class's sysfs interface.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
Acked-by: Moritz Fischer <moritz.fisc...@ettus.com>
--
v15: Document added in v15 of patch set
v16: No change to this patch in v16 of patch set
v17: No change to this
* fpga_bridges_put
Signed-off-by: Alan Tull <at...@opensource.altera.com>
---
v2: Minor cleanup
v12: Bump version to line up with simple fpga bus
Remove sysfs
Improve get/put functions, get the low level driver too.
Clean up class implementation
Add kernel doc documentation
github.com/pantoniou/linux-beagle-track-mainline
Alan
Alan Tull (9):
fpga: add bindings document for fpga region
doc: fpga-mgr: add fpga image info to api
add sysfs document for fpga bridge class
fpga-mgr: add fpga image information struct
fpga: add fpga bridge framework
fpga: fpga-regi
during probe. If the property
does not exist, the driver will leave the bridge in its
current state.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
Signed-off-by: Matthew Gerlach <mgerl...@altera.com>
Signed-off-by: Dinh Nguyen <dingu...@opensource.altera.com>
---
v2:
, replacing the 'u32 flag'
parameter with a pointer to struct fpga_image_info.
Subsequent patches fix the existing low level FPGA manager
drivers.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
Acked-by: Moritz Fischer <moritz.fisc...@ettus.com>
---
v19: Added in v19 of this
Add a low level driver for Altera Freeze Bridges to the FPGA Bridge
framework. A freeze bridge is a bridge that exists in the FPGA
fabric to isolate one region of the FPGA from the busses while that
one region is being reprogrammed.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
Add low level driver to support reprogramming FPGAs for Altera
SoCFPGA Arria10.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
Reviewed-by: Moritz Fischer <moritz.fisc...@ettus.com>
---
v19: Added to this patchset as has been changed to use
fpga image inform
times to enable or disable.
This patch documents the change in the FPGA Manager API
functions, replacing the 'u32 flag' parameter with a pointer
to struct fpga_image_info.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
Acked-by: Moritz Fischer <moritz.fisc...@ettus.com>
--
* fpga_bridges_put
Signed-off-by: Alan Tull <at...@opensource.altera.com>
---
v2: Minor cleanup
v12: Bump version to line up with simple fpga bus
Remove sysfs
Improve get/put functions, get the low level driver too.
Clean up class implementation
Add kernel doc documentation
FPGA Regions support programming FPGA under control of the Device
Tree.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
---
v9: initial version (this patch added during rest of patchset's v9)
v10: request deferral if fpga mgr or bridges not available yet
cleanup as fpga manage
New bindings document for FPGA Region to support programming
FPGA's under Device Tree control
Signed-off-by: Alan Tull <at...@opensource.altera.com>
Signed-off-by: Moritz Fischer <moritz.fisc...@ettus.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
v9: initial version adde
* Pantelis' configfs interface patches and fixes
https://github.com/pantoniou/linux-beagle-track-mainline
Alan
Alan Tull (10):
fpga: add bindings document for fpga region
doc: fpga-mgr: add fpga image info to api
add bindings document for altera freeze bridge
add sysfs document for f
times to enable or disable.
This patch documents the change in the FPGA Manager API
functions, replacing the 'u32 flag' parameter with a pointer
to struct fpga_image_info.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
---
v19: Added in v19 of this patchset
v20: No change for this
Add bindings document for the Altera Freeze Bridge. A Freeze
Bridge is used to gate traffic to/from a region of a FPGA
such that that region can be reprogrammed. The Freeze Bridge
exist in FPGA fabric that is not currently being reconfigured.
Signed-off-by: Alan Tull
, replacing the 'u32 flag'
parameter with a pointer to struct fpga_image_info.
Subsequent patches fix the existing low level FPGA manager
drivers.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
---
v19: Added in v19 of this patchset
v20: Squashed patches that change API for socfpga an
during probe. If the property
does not exist, the driver will leave the bridge in its
current state.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
Signed-off-by: Matthew Gerlach <mgerl...@altera.com>
Signed-off-by: Dinh Nguyen <dingu...@opensource.altera.com>
---
v2:
Add a low level driver for Altera Freeze Bridges to the FPGA Bridge
framework. A freeze bridge is a bridge that exists in the FPGA
fabric to isolate one region of the FPGA from the busses while that
one region is being reprogrammed.
Signed-off-by: Alan Tull <at...@opensource.altera.com>
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