Re: [RFC PATCH 00/11] pci: support for configurable PCI endpoint
On Mon, Sep 26, 2016 at 11:38:41AM +0530, Kishon Vijay Abraham I wrote: > > Ok, so in theory there can be other hardware (and quite likely is) > > that supports multiple functions, and we can extend the framework > > to support them without major obstacles, but your hardware doesn't, > > so you kept it simple with one hardcoded function, right? > > right, PCIe can have upto 8 functions. So the issues with the current > framework > has to be fixed. I don't expect major obstacles with this as of now. I wouldn't be too worried about. We have two kinds of functions in PCIe: physical functions, or virtual functions using SR-IOV. For the first one we pretty much just need the controller driver to report them separately as there is almost no interaction between functions. SR-IOV support will be more interesting as the physical functions controls creation of the associated virtual functions. I'd like to defer that problem until we get hold of a software programmable controller that supports SR-IOV and has open documentation. (That beeing said, if someone has a pointer to such a beast send it my way!) > > We should still find out whether it's important that you can have > > a single PCI function with a software multi-function support of some > > sort. We'd still be limited to six BARs in total, and would also need > > something to identify those sub-functions, so implementing that might > > get quite hairy. > > > > Possibly this could be done at a higher level, e.g. by implementing > > a PCI-virtio multiplexer that can host multiple virtio based devices > > inside of a single PCI function. If we think that would be a good idea, > > we should make sure the configfs interface is extensible enough to > > handle that. > > Okay. So here the main function (actual PCI function) *can* perform the work > of > virtio muliplexer if the platform wants to support sub-functions or it can be > a > normal PCI function. right? I really don't think we should be worried about this multiplexer. It's not something real PCIe devices do (sane ones anyway, the rest is handled by ad-hoc multiplexers), and we should avoid creating our own magic periphals for it. > > One use case I have in mind for this is to have a PCI function that > > can use virtio to provide rootfs (virtio-blk or 9pfs), network > > and console to the system that implements the PCI function (note > > that this is the opposite direction of what almost everyone else > > uses PCI devices for). > > Do you mean the virtio should actually be in the host side? Even here the > system that implements PCI function should have multiple functions right? (one > for network, other for console etc..). So there should be a virtio multiplexer > both in the host side and in the device side? We already support virtio over phsysical PCIe buses to support intel MIC devices. Take a look at drivers/misc/mic/bus/vop_bus.c and drivers/misc/mic/vop (yes, what a horrible place for that code, not my fault) -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC PATCH 00/11] pci: support for configurable PCI endpoint
Hi Arnd,
On Monday 26 September 2016 11:38 AM, Kishon Vijay Abraham I wrote:
> Hi Arnd,
>
> On Thursday 22 September 2016 07:04 PM, Arnd Bergmann wrote:
>> On Thursday, September 15, 2016 2:03:05 PM CEST Kishon Vijay Abraham I wrote:
>>> On Wednesday 14 September 2016 06:55 PM, Arnd Bergmann wrote:
On Wednesday, September 14, 2016 10:41:56 AM CEST Kishon Vijay Abraham I
wrote:
I've added the drivers/ntb maintainers to Cc, given that there is
a certain degree of overlap between your work and the existing
code, I think they should be part of the discussion.
> Known Limitation:
> *) Does not support multi-function devices
If I understand it right, this was a problem for USB and adding
it later made it somewhat inconsistent. Maybe we can at least
try to come up with an idea of how multi-function devices
could be handled even if we don't implement it until someone
actually needs it.
>>>
>>> Actually IMO multi-function device in PCI should be much simpler than it is
>>> for
>>> USB. In the case of USB, all the functions in a multi-function device will
>>> share the same *usb configuration* . (USB device can have multiple
>>> configuration but only one can be enabled at a time). A multi-function USB
>>> device will still have a single vendor-id/product-id/class... So I think a
>>> separate library (composite.c) in USB makes sense.
>>
>> Ok, makes sense.
>>
>>> But in the case of PCI, every function can be treated independently since
>>> all
>>> the functions have it's own 4KB configuration space. Each function can be
>>> configured independently. Each can have it's own
>>> vendor-id/product-id/class..
>>> I'm not sure if we'll need a separate library for PCI like we have for USB.
>>
>> I think it depends on whether we want to add the software multi-function
>> support you mention.
>>
>>> Now the restriction for not allowing multi-function device is because of the
>>> following structure definition.
>>>
>>> struct pci_epc {
>>> ..
>>> struct pci_epf *epf;
>>> ..
>>> };
>>>
>>> EPC has a single reference to EPF and it is used *only* to notify the
>>> function
>>> driver when the link is up. (If this can be changed to use notification
>>> mechanism, multi-function devices can be supported here)
>>>
>>> One more place where this restriction arises is in designware driver
>>>
>>> struct dw_pcie_ep {
>>> ..
>>> u8 bar_to_atu[6];
>>> ..
>>> };
>>>
>>> We use single ATU window to configure a BAR (in BAR). If there are multiple
>>> functions, then this should also be modified since each function has 6 BARs.
>>>
>>> This can be fixed without much effort unless some other issue props up.
>>
>> Ok.
>>
Is your hardware able to make the PCIe endpoint look like
a device with multiple PCI functions, or would one have to
do this in software inside of a single PCI function if we
ever need it?
>>>
>>> The hardware I have doesn't support multiple PCI functions (like having a
>>> separate configuration space for each function). It has a dedicated space
>>> for
>>> configuration space supporting only one function. [Section 24.9.7.3.2
>>> PCIe_SS_EP_CFG_DBICS Register Description in [1]].
>>>
>>> yeah, it has to be done in software (but that won't be multi-function
>>> device in
>>> PCI terms).
>>>
>>> [1] -> http://www.ti.com/lit/ug/spruhz6g/spruhz6g.pdf
>>
>> Ok, so in theory there can be other hardware (and quite likely is)
>> that supports multiple functions, and we can extend the framework
>> to support them without major obstacles, but your hardware doesn't,
>> so you kept it simple with one hardcoded function, right?
>
> right, PCIe can have upto 8 functions. So the issues with the current
> framework
> has to be fixed. I don't expect major obstacles with this as of now.
>>
>> Seems completely reasonable to me.
>>
> TODO:
> *) access buffers in RC
> *) raise MSI interrupts
> *) Enable user space control for the RC side PCI driver
The user space control would end up just being one of several
gadget drivers, right? E.g. gadget drivers for standard hardware
(8250 uart, ATA, NVMe, some ethernet) could be done as kernel
drivers while a user space driver can be used for things that
are more unusual and that don't need to interface to another
part of the kernel?
>>>
>>> Actually I didn't mean that. It was more with respect to the host side PCI
>>> test
>>> driver (drivers/misc/pci_endpoint_test.c). Right now it validates BAR, irq
>>> itself. I wanted to change this so that the user controls which tests to
>>> run.
>>> (Like for USB gadget zero tests, testusb.c invokes ioctls to perform various
>>> tests). Similarly I want to have a userspace program invoke
>>> pci_endpoint_test
>>> to perform various PCI tests.
>>
>> Ok, I see. So what I described above would be yet another function
>> driver that can be implemented, but so far, you have
Re: [RFC PATCH 00/11] pci: support for configurable PCI endpoint
Hi Arnd,
On Thursday 22 September 2016 07:04 PM, Arnd Bergmann wrote:
> On Thursday, September 15, 2016 2:03:05 PM CEST Kishon Vijay Abraham I wrote:
>> On Wednesday 14 September 2016 06:55 PM, Arnd Bergmann wrote:
>>> On Wednesday, September 14, 2016 10:41:56 AM CEST Kishon Vijay Abraham I
>>> wrote:
>>> I've added the drivers/ntb maintainers to Cc, given that there is
>>> a certain degree of overlap between your work and the existing
>>> code, I think they should be part of the discussion.
>>>
Known Limitation:
*) Does not support multi-function devices
>>>
>>> If I understand it right, this was a problem for USB and adding
>>> it later made it somewhat inconsistent. Maybe we can at least
>>> try to come up with an idea of how multi-function devices
>>> could be handled even if we don't implement it until someone
>>> actually needs it.
>>
>> Actually IMO multi-function device in PCI should be much simpler than it is
>> for
>> USB. In the case of USB, all the functions in a multi-function device will
>> share the same *usb configuration* . (USB device can have multiple
>> configuration but only one can be enabled at a time). A multi-function USB
>> device will still have a single vendor-id/product-id/class... So I think a
>> separate library (composite.c) in USB makes sense.
>
> Ok, makes sense.
>
>> But in the case of PCI, every function can be treated independently since all
>> the functions have it's own 4KB configuration space. Each function can be
>> configured independently. Each can have it's own vendor-id/product-id/class..
>> I'm not sure if we'll need a separate library for PCI like we have for USB.
>
> I think it depends on whether we want to add the software multi-function
> support you mention.
>
>> Now the restriction for not allowing multi-function device is because of the
>> following structure definition.
>>
>> struct pci_epc {
>> ..
>> struct pci_epf *epf;
>> ..
>> };
>>
>> EPC has a single reference to EPF and it is used *only* to notify the
>> function
>> driver when the link is up. (If this can be changed to use notification
>> mechanism, multi-function devices can be supported here)
>>
>> One more place where this restriction arises is in designware driver
>>
>> struct dw_pcie_ep {
>> ..
>> u8 bar_to_atu[6];
>> ..
>> };
>>
>> We use single ATU window to configure a BAR (in BAR). If there are multiple
>> functions, then this should also be modified since each function has 6 BARs.
>>
>> This can be fixed without much effort unless some other issue props up.
>
> Ok.
>
>>>
>>> Is your hardware able to make the PCIe endpoint look like
>>> a device with multiple PCI functions, or would one have to
>>> do this in software inside of a single PCI function if we
>>> ever need it?
>>
>> The hardware I have doesn't support multiple PCI functions (like having a
>> separate configuration space for each function). It has a dedicated space for
>> configuration space supporting only one function. [Section 24.9.7.3.2
>> PCIe_SS_EP_CFG_DBICS Register Description in [1]].
>>
>> yeah, it has to be done in software (but that won't be multi-function device
>> in
>> PCI terms).
>>
>> [1] -> http://www.ti.com/lit/ug/spruhz6g/spruhz6g.pdf
>
> Ok, so in theory there can be other hardware (and quite likely is)
> that supports multiple functions, and we can extend the framework
> to support them without major obstacles, but your hardware doesn't,
> so you kept it simple with one hardcoded function, right?
right, PCIe can have upto 8 functions. So the issues with the current framework
has to be fixed. I don't expect major obstacles with this as of now.
>
> Seems completely reasonable to me.
>
TODO:
*) access buffers in RC
*) raise MSI interrupts
*) Enable user space control for the RC side PCI driver
>>>
>>> The user space control would end up just being one of several
>>> gadget drivers, right? E.g. gadget drivers for standard hardware
>>> (8250 uart, ATA, NVMe, some ethernet) could be done as kernel
>>> drivers while a user space driver can be used for things that
>>> are more unusual and that don't need to interface to another
>>> part of the kernel?
>>
>> Actually I didn't mean that. It was more with respect to the host side PCI
>> test
>> driver (drivers/misc/pci_endpoint_test.c). Right now it validates BAR, irq
>> itself. I wanted to change this so that the user controls which tests to run.
>> (Like for USB gadget zero tests, testusb.c invokes ioctls to perform various
>> tests). Similarly I want to have a userspace program invoke pci_endpoint_test
>> to perform various PCI tests.
>
> Ok, I see. So what I described above would be yet another function
> driver that can be implemented, but so far, you have not planned
> to do that because there was not need, right?
right. I felt pci_endpoint_test is the generic function that would be of
interest to all the vendors. Any new function can be added by taking
Re: [RFC PATCH 00/11] pci: support for configurable PCI endpoint
On Thursday, September 15, 2016 2:03:05 PM CEST Kishon Vijay Abraham I wrote:
> On Wednesday 14 September 2016 06:55 PM, Arnd Bergmann wrote:
> > On Wednesday, September 14, 2016 10:41:56 AM CEST Kishon Vijay Abraham I
> > wrote:
> > I've added the drivers/ntb maintainers to Cc, given that there is
> > a certain degree of overlap between your work and the existing
> > code, I think they should be part of the discussion.
> >
> >> Known Limitation:
> >>*) Does not support multi-function devices
> >
> > If I understand it right, this was a problem for USB and adding
> > it later made it somewhat inconsistent. Maybe we can at least
> > try to come up with an idea of how multi-function devices
> > could be handled even if we don't implement it until someone
> > actually needs it.
>
> Actually IMO multi-function device in PCI should be much simpler than it is
> for
> USB. In the case of USB, all the functions in a multi-function device will
> share the same *usb configuration* . (USB device can have multiple
> configuration but only one can be enabled at a time). A multi-function USB
> device will still have a single vendor-id/product-id/class... So I think a
> separate library (composite.c) in USB makes sense.
Ok, makes sense.
> But in the case of PCI, every function can be treated independently since all
> the functions have it's own 4KB configuration space. Each function can be
> configured independently. Each can have it's own vendor-id/product-id/class..
> I'm not sure if we'll need a separate library for PCI like we have for USB.
I think it depends on whether we want to add the software multi-function
support you mention.
> Now the restriction for not allowing multi-function device is because of the
> following structure definition.
>
> struct pci_epc {
> ..
> struct pci_epf *epf;
> ..
> };
>
> EPC has a single reference to EPF and it is used *only* to notify the function
> driver when the link is up. (If this can be changed to use notification
> mechanism, multi-function devices can be supported here)
>
> One more place where this restriction arises is in designware driver
>
> struct dw_pcie_ep {
> ..
> u8 bar_to_atu[6];
> ..
> };
>
> We use single ATU window to configure a BAR (in BAR). If there are multiple
> functions, then this should also be modified since each function has 6 BARs.
>
> This can be fixed without much effort unless some other issue props up.
Ok.
> >
> > Is your hardware able to make the PCIe endpoint look like
> > a device with multiple PCI functions, or would one have to
> > do this in software inside of a single PCI function if we
> > ever need it?
>
> The hardware I have doesn't support multiple PCI functions (like having a
> separate configuration space for each function). It has a dedicated space for
> configuration space supporting only one function. [Section 24.9.7.3.2
> PCIe_SS_EP_CFG_DBICS Register Description in [1]].
>
> yeah, it has to be done in software (but that won't be multi-function device
> in
> PCI terms).
>
> [1] -> http://www.ti.com/lit/ug/spruhz6g/spruhz6g.pdf
Ok, so in theory there can be other hardware (and quite likely is)
that supports multiple functions, and we can extend the framework
to support them without major obstacles, but your hardware doesn't,
so you kept it simple with one hardcoded function, right?
Seems completely reasonable to me.
> >> TODO:
> >>*) access buffers in RC
> >>*) raise MSI interrupts
> >>*) Enable user space control for the RC side PCI driver
> >
> > The user space control would end up just being one of several
> > gadget drivers, right? E.g. gadget drivers for standard hardware
> > (8250 uart, ATA, NVMe, some ethernet) could be done as kernel
> > drivers while a user space driver can be used for things that
> > are more unusual and that don't need to interface to another
> > part of the kernel?
>
> Actually I didn't mean that. It was more with respect to the host side PCI
> test
> driver (drivers/misc/pci_endpoint_test.c). Right now it validates BAR, irq
> itself. I wanted to change this so that the user controls which tests to run.
> (Like for USB gadget zero tests, testusb.c invokes ioctls to perform various
> tests). Similarly I want to have a userspace program invoke pci_endpoint_test
> to perform various PCI tests.
Ok, I see. So what I described above would be yet another function
driver that can be implemented, but so far, you have not planned
to do that because there was not need, right?
> >
> >>*) Adapt all other users of designware to use the new design (only
> >> dra7xx has been adapted)
> >
> > I don't fully understand this part. Does every designware based
> > driver need modifications, or are the changes to the
> > generic parts of the designware driver enough to make it
> > work for the simpler platforms?
>
> I have changed the core designware driver structures (like previously the
> platform drivers will only use
Re: [RFC PATCH 00/11] pci: support for configurable PCI endpoint
Hi Arnd,
On Wednesday 14 September 2016 06:55 PM, Arnd Bergmann wrote:
> On Wednesday, September 14, 2016 10:41:56 AM CEST Kishon Vijay Abraham I
> wrote:
>> This patch series
>> *) adds PCI endpoint core layer
>> *) modifies designware/dra7xx driver to be configured in EP mode
>> *) adds a PCI endpoint *test* function driver
>
> Hi Kishon,
>
> I think this is a great start, thanks for posting early with a clear
> list of limitations and TODO items.
Thank you :-)
>
> I've added the drivers/ntb maintainers to Cc, given that there is
> a certain degree of overlap between your work and the existing
> code, I think they should be part of the discussion.
>
>> Known Limitation:
>> *) Does not support multi-function devices
>
> If I understand it right, this was a problem for USB and adding
> it later made it somewhat inconsistent. Maybe we can at least
> try to come up with an idea of how multi-function devices
> could be handled even if we don't implement it until someone
> actually needs it.
Actually IMO multi-function device in PCI should be much simpler than it is for
USB. In the case of USB, all the functions in a multi-function device will
share the same *usb configuration* . (USB device can have multiple
configuration but only one can be enabled at a time). A multi-function USB
device will still have a single vendor-id/product-id/class... So I think a
separate library (composite.c) in USB makes sense.
But in the case of PCI, every function can be treated independently since all
the functions have it's own 4KB configuration space. Each function can be
configured independently. Each can have it's own vendor-id/product-id/class..
I'm not sure if we'll need a separate library for PCI like we have for USB.
Now the restriction for not allowing multi-function device is because of the
following structure definition.
struct pci_epc {
..
struct pci_epf *epf;
..
};
EPC has a single reference to EPF and it is used *only* to notify the function
driver when the link is up. (If this can be changed to use notification
mechanism, multi-function devices can be supported here)
One more place where this restriction arises is in designware driver
struct dw_pcie_ep {
..
u8 bar_to_atu[6];
..
};
We use single ATU window to configure a BAR (in BAR). If there are multiple
functions, then this should also be modified since each function has 6 BARs.
This can be fixed without much effort unless some other issue props up.
>
> Is your hardware able to make the PCIe endpoint look like
> a device with multiple PCI functions, or would one have to
> do this in software inside of a single PCI function if we
> ever need it?
The hardware I have doesn't support multiple PCI functions (like having a
separate configuration space for each function). It has a dedicated space for
configuration space supporting only one function. [Section 24.9.7.3.2
PCIe_SS_EP_CFG_DBICS Register Description in [1]].
yeah, it has to be done in software (but that won't be multi-function device in
PCI terms).
[1] -> http://www.ti.com/lit/ug/spruhz6g/spruhz6g.pdf
>
>> TODO:
>> *) access buffers in RC
>> *) raise MSI interrupts
>> *) Enable user space control for the RC side PCI driver
>
> The user space control would end up just being one of several
> gadget drivers, right? E.g. gadget drivers for standard hardware
> (8250 uart, ATA, NVMe, some ethernet) could be done as kernel
> drivers while a user space driver can be used for things that
> are more unusual and that don't need to interface to another
> part of the kernel?
Actually I didn't mean that. It was more with respect to the host side PCI test
driver (drivers/misc/pci_endpoint_test.c). Right now it validates BAR, irq
itself. I wanted to change this so that the user controls which tests to run.
(Like for USB gadget zero tests, testusb.c invokes ioctls to perform various
tests). Similarly I want to have a userspace program invoke pci_endpoint_test
to perform various PCI tests.
>
>> *) Adapt all other users of designware to use the new design (only
>> dra7xx has been adapted)
>
> I don't fully understand this part. Does every designware based
> driver need modifications, or are the changes to the
> generic parts of the designware driver enough to make it
> work for the simpler platforms?
I have changed the core designware driver structures (like previously the
platform drivers will only use pcie_port, but now I introduced struct dw_pcie
to support both host and endpoint). This will break (compilation failure) all
the designware based drivers (except dra7xx). All these drivers should be
adapted to the new change (even if they work only in host mode these has to be
adapted).
>
>> HOW TO:
>>
>> ON THE EP SIDE:
>> ***
>>
>> /* EP function is configured using configfs */
>> # mount -t configfs none /sys/kernel/config
>>
>> /* PCI EP core layer creates "pci_ep" entry in configfs */
Re: [RFC PATCH 00/11] pci: support for configurable PCI endpoint
On Wednesday, September 14, 2016 10:41:56 AM CEST Kishon Vijay Abraham I wrote:
> This patch series
> *) adds PCI endpoint core layer
> *) modifies designware/dra7xx driver to be configured in EP mode
> *) adds a PCI endpoint *test* function driver
Hi Kishon,
I think this is a great start, thanks for posting early with a clear
list of limitations and TODO items.
I've added the drivers/ntb maintainers to Cc, given that there is
a certain degree of overlap between your work and the existing
code, I think they should be part of the discussion.
> Known Limitation:
> *) Does not support multi-function devices
If I understand it right, this was a problem for USB and adding
it later made it somewhat inconsistent. Maybe we can at least
try to come up with an idea of how multi-function devices
could be handled even if we don't implement it until someone
actually needs it.
Is your hardware able to make the PCIe endpoint look like
a device with multiple PCI functions, or would one have to
do this in software inside of a single PCI function if we
ever need it?
> TODO:
> *) access buffers in RC
> *) raise MSI interrupts
> *) Enable user space control for the RC side PCI driver
The user space control would end up just being one of several
gadget drivers, right? E.g. gadget drivers for standard hardware
(8250 uart, ATA, NVMe, some ethernet) could be done as kernel
drivers while a user space driver can be used for things that
are more unusual and that don't need to interface to another
part of the kernel?
> *) Adapt all other users of designware to use the new design (only
> dra7xx has been adapted)
I don't fully understand this part. Does every designware based
driver need modifications, or are the changes to the
generic parts of the designware driver enough to make it
work for the simpler platforms?
> HOW TO:
>
> ON THE EP SIDE:
> ***
>
> /* EP function is configured using configfs */
> # mount -t configfs none /sys/kernel/config
>
> /* PCI EP core layer creates "pci_ep" entry in configfs */
> # cd /sys/kernel/config/pci_ep/
>
> /*
> * This is the 1st step in creating an endpoint function. This
> * creates the endpoint function device *instance*. The string
> * before the . suffix will identify the driver this
> * EP function will bind to.
> * Just pci_epf_test is also valid. The . suffix is used
> * if there are multiple PCI controllers and all of them wants
> * to use the same function.
> */
> # mkdir pci_epf_test.0
I haven't used USB gadgets, but I assume this is modeled around
the same interface. If there are notable differences, please mention
what they are. Otherwise the general concept seems rather nice to me.
> drivers/pci/{host => controller}/Kconfig | 109 +-
> drivers/pci/{host => controller}/Makefile |2 +
> drivers/pci/{host => controller}/pci-aardvark.c|0
> drivers/pci/{host => controller}/pci-dra7xx.c | 340 +
> drivers/pci/{host => controller}/pci-exynos.c |0
> drivers/pci/{host => controller}/pci-host-common.c |0
> .../pci/{host => controller}/pci-host-generic.c|0
> drivers/pci/{host => controller}/pci-hyperv.c |0
> drivers/pci/{host => controller}/pci-imx6.c|0
> drivers/pci/{host => controller}/pci-keystone-dw.c |0
> drivers/pci/{host => controller}/pci-keystone.c|0
> drivers/pci/{host => controller}/pci-keystone.h|0
Maybe it's better to wait before moving it around, this will make
it harder for you to rebase the patch series while you are working on
it and other people are working on the existing code.
I'd suggest dropping the rename patches for the moment and just work
in drivers/pci/host.
Let's talk (high-level) about the DT binding. I see that the way
you have done it here, one will need to have a different .dtb file
for a machine depending on whether the PCIe is used in host or
endpoint mode. The advantage of this way is that it's a much
cleaner binding (PCIe host bindings are a mess, and adding more
options to it will only make it worse), the downside is that
you can't decide at runtime what you want to use it for. E.g.
connecting two identical machines over PCIe requires deciding
in the bootloader which one is the endpoint, or using DT
overlays, which may be awkward for some users. Is this a realistic
use case, or do you expect that all machines will only ever be
used in one of the two ways?
Arnd
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[RFC PATCH 00/11] pci: support for configurable PCI endpoint
This patch series
*) adds PCI endpoint core layer
*) modifies designware/dra7xx driver to be configured in EP mode
*) adds a PCI endpoint *test* function driver
Known Limitation:
*) Does not support multi-function devices
TODO:
*) access buffers in RC
*) raise MSI interrupts
*) Enable user space control for the RC side PCI driver
*) Adapt all other users of designware to use the new design (only
dra7xx has been adapted)
HOW TO:
ON THE EP SIDE:
***
/* EP function is configured using configfs */
# mount -t configfs none /sys/kernel/config
/* PCI EP core layer creates "pci_ep" entry in configfs */
# cd /sys/kernel/config/pci_ep/
/*
* This is the 1st step in creating an endpoint function. This
* creates the endpoint function device *instance*. The string
* before the . suffix will identify the driver this
* EP function will bind to.
* Just pci_epf_test is also valid. The . suffix is used
* if there are multiple PCI controllers and all of them wants
* to use the same function.
*/
# mkdir pci_epf_test.0
/*
* When the above command is given, the function device will
* also be bound to a function driver. To find the list of
* function drivers available in the system, use the following
* command. To create a new driver, the following can be referred
* drivers/pci/endpoint/functions/pci-epf-test.c
*/
# ls /sys/bus/pci-epf/drivers
pci_epf_test
/* Now configure the endpoint function */
# cd pci_epf_test.0
/* These are the fields that can be configured */
# ls
baseclass_codefunction revid vendorid
cache_line_size interrupt_pin subclass_code
deviceid peripheralsubsys_id
epc progif_code subsys_vendor_id
/* The function driver will populate these fields with default values */
# cat vendorid
0x
# cat interrupt_pin
0x0001
/* The user can configure any of these fields */
# echo 0x104c > vendorid
/*
* Next is binding this function driver to the controller driver. In
* order to find the possible controller drivers that this function
* driver can be bound to, the following sysfs entry can be used
*/
# ls /sys/class/pci_epc/
5100.pci
/* Now bind the function driver to the controller driver */
# echo "5100.pcie" > epc
[ 494.743487] dra7-pcie 5100.pcie: no free inbound window
[ 494.749367] pci_epf_test pci_epf_test.0: failed to set BAR4
[ 494.755238] dra7-pcie 5100.pcie: no free inbound window
[ 494.761451] pci_epf_test pci_epf_test.0: failed to set BAR5
/*
* the above error messages are due to non availability of free
* inbound windows. So the function drivers in dra7xx can use
* only 4 (BAR0..BAR3) BARs
*/
/** PCI endpoint is configured **/
ON THE HOST SIDE:
*
# modprobe pci_endpoint_test
[8.197560] ** Testing pci-endpoint-test Device **
[9.056990] Reset: OKAY
[9.059753] BAR1 OKAY
[9.062419] BAR2 OKAY
[9.069506] BAR3 OKAY
[9.071880] BAR4 NOT OKAY
[9.074618] BAR5 NOT OKAY
[9.379257] Legacy IRQ: OKAY
[9.382281] ** End Test **
/*
* Rightnow these tests gets executed as soon as the pci_endpoint_test
* module gets inserted. These will be modified so that user/user script
* can control this. Once the functionality for EP to access RC buffer
* is added, more tests can be added including throughput measurement tests.
*/
Kishon Vijay Abraham I (11):
pci: endpoint: add EP core layer to enable EP controller and EP
functions
pci: endpoint: introduce configfs entry for configuring EP functions
Documentation: PCI: guide to use PCI Endpoint Core Layer
pci: endpoint: functions: add an EP function to test PCI
pci: rename *host* directory to *controller*
pci: controller: split designware into *core* and *host*
pci: controller: designware: Add EP mode support
pci: controller: dra7xx: Add EP mode support
misc: add a new host side PCI endpoint test driver
ARM: dts: DRA7: Modify pcie1 dt node for EP mode
HACK: pci: controller: dra7xx: disable smart idle
Documentation/PCI/00-INDEX |5 +
Documentation/PCI/pci-endpoint.txt | 199 ++
Documentation/PCI/pci-test.txt | 79
.../devicetree/bindings/pci/designware-pcie.txt| 26 +-
Documentation/devicetree/bindings/pci/ti-pci.txt | 30 +-
MAINTAINERS| 50 +--
arch/arm/boot/dts/dra7.dtsi| 43 +--
drivers/Makefile |4 +
drivers/misc/Kconfig |7 +
drivers/misc/Makefile |1 +
drivers/misc/pci_endpoint_test.c | 291 +++
drivers/pci/Kconfig|3 +-
drivers/pci/Makefile |3 -
drivers/pci/{host => controller}/Kconfig | 109
