Re: [PATCH v20 10/10] fpga-manager: Add Socfpga Arria10 support

[atull]

On Tue, 18 Oct 2016, Moritz Fischer wrote:

> On Mon, Oct 17, 2016 at 11:09:41AM -0500, Alan Tull wrote:
> > Add low level driver to support reprogramming FPGAs for Altera
> > SoCFPGA Arria10.
> > 
> > Signed-off-by: Alan Tull 
> 
> Reviewed-by: Moritz Fischer 

> > +
> > +MODULE_AUTHOR("Alan Tull ");
> > +MODULE_DESCRIPTION("SoCFPGA Arria10 FPGA Manager");
> > +MODULE_LICENSE("GPL v2");
> > -- 
> > 2.10.1
> > 
> 
> Looking good,
> 
> Moritz
> 

Hi Moritz,

Thanks!

Alan
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Re: [PATCH v20 10/10] fpga-manager: Add Socfpga Arria10 support

[Moritz Fischer]

On Mon, Oct 17, 2016 at 11:09:41AM -0500, Alan Tull wrote:
> Add low level driver to support reprogramming FPGAs for Altera
> SoCFPGA Arria10.
> 
> Signed-off-by: Alan Tull 

Reviewed-by: Moritz Fischer 
> ---
> v19: Added to this patchset as has been changed to use
>fpga image information struct
>  a checkpatch fix of a block comment
>  do not use clk_put because we are using devm_clk_get
> v20: use regmap_read_poll_timeout
>  Add some macros/comments
>  remove some debug prints
> ---
>  drivers/fpga/Kconfig   |   6 +
>  drivers/fpga/Makefile  |   1 +
>  drivers/fpga/socfpga-a10.c | 556 
> +
>  3 files changed, 563 insertions(+)
>  create mode 100644 drivers/fpga/socfpga-a10.c
> 
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index 8fe6a84..889e4c3 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -26,6 +26,12 @@ config FPGA_MGR_SOCFPGA
>   help
> FPGA manager driver support for Altera SOCFPGA.
>  
> +config FPGA_MGR_SOCFPGA_A10
> + tristate "Altera SoCFPGA Arria10"
> + depends on ARCH_SOCFPGA
> + help
> +   FPGA manager driver support for Altera Arria10 SoCFPGA.
> +
>  config FPGA_MGR_ZYNQ_FPGA
>   tristate "Xilinx Zynq FPGA"
>   depends on ARCH_ZYNQ || COMPILE_TEST
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index a6f874d..8df07bc 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -7,6 +7,7 @@ obj-$(CONFIG_FPGA)+= fpga-mgr.o
>  
>  # FPGA Manager Drivers
>  obj-$(CONFIG_FPGA_MGR_SOCFPGA)   += socfpga.o
> +obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)   += socfpga-a10.o
>  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
>  
>  # FPGA Bridge Drivers
> diff --git a/drivers/fpga/socfpga-a10.c b/drivers/fpga/socfpga-a10.c
> new file mode 100644
> index 000..ccd9fb2
> --- /dev/null
> +++ b/drivers/fpga/socfpga-a10.c
> @@ -0,0 +1,556 @@
> +/*
> + * FPGA Manager Driver for Altera Arria10 SoCFPGA
> + *
> + * Copyright (C) 2015-2016 Altera Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along 
> with
> + * this program.  If not, see .
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define A10_FPGAMGR_DCLKCNT_OFST 0x08
> +#define A10_FPGAMGR_DCLKSTAT_OFST0x0c
> +#define A10_FPGAMGR_IMGCFG_CTL_00_OFST   0x70
> +#define A10_FPGAMGR_IMGCFG_CTL_01_OFST   0x74
> +#define A10_FPGAMGR_IMGCFG_CTL_02_OFST   0x78
> +#define A10_FPGAMGR_IMGCFG_STAT_OFST 0x80
> +
> +#define A10_FPGAMGR_DCLKSTAT_DCLKDONEBIT(0)
> +
> +#define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIGBIT(0)
> +#define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUSBIT(1)
> +#define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONEBIT(2)
> +#define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIGBIT(8)
> +#define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE BIT(16)
> +#define A10_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE BIT(24)
> +
> +#define A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG BIT(0)
> +#define A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST BIT(16)
> +#define A10_FPGAMGR_IMGCFG_CTL_01_S2F_NCEBIT(24)
> +
> +#define A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRLBIT(0)
> +#define A10_FPGAMGR_IMGCFG_CTL_02_CDRATIO_MASK   (BIT(16) | 
> BIT(17))
> +#define A10_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SHIFT  16
> +#define A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH   BIT(24)
> +#define A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SHIFT 24
> +
> +#define A10_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERRORBIT(0)
> +#define A10_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE   BIT(1)
> +#define A10_FPGAMGR_IMGCFG_STAT_F2S_USERMODE BIT(2)
> +#define A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN  BIT(4)
> +#define A10_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN  BIT(6)
> +#define A10_FPGAMGR_IMGCFG_STAT_F2S_PR_READY BIT(9)
> +#define A10_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE  BIT(10)
> +#define A10_FPGAMGR_IMGCFG_STAT_F2S_