On Sat, Aug 12, 2017 at 12:51 PM, wrote:
> 在 2017-08-12 12:04,Chen-Yu Tsai 写道:
>>
>> On Sat, Jul 22, 2017 at 11:00 AM, wrote:
>>>
>>> 在 2017-05-29 15:34,Chen-Yu Tsai 写道:
Hi,
On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng
在 2017-08-12 12:04,Chen-Yu Tsai 写道:
On Sat, Jul 22, 2017 at 11:00 AM, wrote:
在 2017-05-29 15:34,Chen-Yu Tsai 写道:
Hi,
On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote:
[...]
+
+/*
+ * For the special bit in gate part, please see the BSP source code
at
+ *
On Sat, Aug 12, 2017 at 12:04 PM, wrote:
> 在 2017-05-29 15:34,Chen-Yu Tsai 写道:
>>
>> Hi,
>>
>> On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote:
>>>
>>> Allwinner R40 SoC have a clock controller module in the style of the
>>> SoCs beyond sun6i, however, it's more
On Sat, Jul 22, 2017 at 11:00 AM, wrote:
> 在 2017-05-29 15:34,Chen-Yu Tsai 写道:
>>
>> Hi,
>>
>> On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote:
[...]
>>> +
>>> +/*
>>> + * For the special bit in gate part, please see the BSP source code at
>>> + *
>>>
在 2017-05-29 15:34,Chen-Yu Tsai 写道:
Hi,
On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote:
Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.
Add support for it.
Signed-off-by: Icenowy Zheng
Hi,
On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote:
> Allwinner R40 SoC have a clock controller module in the style of the
> SoCs beyond sun6i, however, it's more rich and complex.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng
> ---
> Changes in v3:
>