> it
> can update the memory pointed to by GHES->ErrorStatusAddress with the location
> of the CPER records and invoke the Notification method for this GHES. (SEI,
> SEA,
> IRQ etc). We should always get a complete set of CPER records to describe the
> error.
>
Does
Reviewed-by: Xie XiuQi <xiexi...@huawei.com>
On 2017/3/22 6:47, Tyler Baicar wrote:
> Currently there are trace events for the various RAS
> errors with the exception of ARM processor type errors.
> Add a new trace event for such errors so that the user
> will know when they
Hi Steven,
Thanks for you comments. As your suggestion, I've changed it in v2.
>From c29c14c3b960f55beb4c4b22b7aced64fa7daf9a Mon Sep 17 00:00:00 2001
From: Xie XiuQi <xiexi...@huawei.com>
Date: Mon, 13 Mar 2017 15:46:06 +0800
Subject: [PATCH v2] trace: ras: add ARM processor error in
Hi Baicar Tyler,
On 2017/3/13 10:31, Xie XiuQi wrote:
> Hi Baicar Tyler,
>
> On 2017/3/11 2:23, Baicar, Tyler wrote:
>> Hello Xie XiuQi,
>>
>>
>> On 3/9/2017 2:41 AM, Xie XiuQi wrote:
>>> On 2017/3/7 4:45, Tyler Baicar wrote:
>>>> Currently
Hi Baicar Tyler,
On 2017/3/11 2:23, Baicar, Tyler wrote:
> Hello Xie XiuQi,
>
>
> On 3/9/2017 2:41 AM, Xie XiuQi wrote:
>> On 2017/3/7 4:45, Tyler Baicar wrote:
>>> Currently there are trace events for the various RAS
>>> errors with the exception of ARM
->psci_state = proc->psci_state;
> + ),
> +
> + TP_printk("affinity level: %d; MPIDR: %016llx; MIDR: %016llx; "
> + "running state: %d; PSCI state: %d",
> + __entry->affinity, __entry->mpidr, __entry->midr,
