[PATCH 1/2] arm64: account for GICv3 LPI tables in static memblock reserve table

2019-02-15 Thread Ard Biesheuvel
In the irqchip and EFI code, we have what basically amounts to a quirk to work around a peculiarity in the GICv3 architecture, which permits the system memory address of LPI tables to be programmable only once after a CPU reset. This means kexec kernels must use the same memory as the first

Re: [PATCH 1/2] arm64: account for GICv3 LPI tables in static memblock reserve table

2019-02-15 Thread Marc Zyngier
On Thu, 14 Feb 2019 16:55:28 +, Ard Biesheuvel wrote: > > On Thu, 14 Feb 2019 at 16:48, Marc Zyngier wrote: > > > > Hi Ard, > > > > On 13/02/2019 13:27, Ard Biesheuvel wrote: > > > In the irqchip and EFI code, we have what basically amounts to a quirk > > > to work around a peculiarity in

Re: [PATCH 1/2] arm64: account for GICv3 LPI tables in static memblock reserve table

2019-02-14 Thread Ard Biesheuvel
On Thu, 14 Feb 2019 at 16:48, Marc Zyngier wrote: > > Hi Ard, > > On 13/02/2019 13:27, Ard Biesheuvel wrote: > > In the irqchip and EFI code, we have what basically amounts to a quirk > > to work around a peculiarity in the GICv3 architecture, which permits > > the system memory address of LPI

Re: [PATCH 1/2] arm64: account for GICv3 LPI tables in static memblock reserve table

2019-02-14 Thread Marc Zyngier
Hi Ard, On 13/02/2019 13:27, Ard Biesheuvel wrote: > In the irqchip and EFI code, we have what basically amounts to a quirk > to work around a peculiarity in the GICv3 architecture, which permits > the system memory address of LPI tables to be programmable only once > after a CPU reset. This

Re: [PATCH 1/2] arm64: account for GICv3 LPI tables in static memblock reserve table

2019-02-14 Thread Mike Rapoport
On Thu, Feb 14, 2019 at 03:57:35PM +0100, Ard Biesheuvel wrote: > On Thu, 14 Feb 2019 at 09:34, Mike Rapoport wrote: > > > > On Wed, Feb 13, 2019 at 02:27:37PM +0100, Ard Biesheuvel wrote: > > > In the irqchip and EFI code, we have what basically amounts to a quirk > > > to work around a

Re: [PATCH 1/2] arm64: account for GICv3 LPI tables in static memblock reserve table

2019-02-14 Thread Ard Biesheuvel
On Thu, 14 Feb 2019 at 09:34, Mike Rapoport wrote: > > On Wed, Feb 13, 2019 at 02:27:37PM +0100, Ard Biesheuvel wrote: > > In the irqchip and EFI code, we have what basically amounts to a quirk > > to work around a peculiarity in the GICv3 architecture, which permits > > the system memory address

Re: [PATCH 1/2] arm64: account for GICv3 LPI tables in static memblock reserve table

2019-02-14 Thread Will Deacon
On Wed, Feb 13, 2019 at 02:27:37PM +0100, Ard Biesheuvel wrote: > In the irqchip and EFI code, we have what basically amounts to a quirk > to work around a peculiarity in the GICv3 architecture, which permits > the system memory address of LPI tables to be programmable only once > after a CPU

Re: [PATCH 1/2] arm64: account for GICv3 LPI tables in static memblock reserve table

2019-02-14 Thread Mike Rapoport
On Wed, Feb 13, 2019 at 02:27:37PM +0100, Ard Biesheuvel wrote: > In the irqchip and EFI code, we have what basically amounts to a quirk > to work around a peculiarity in the GICv3 architecture, which permits > the system memory address of LPI tables to be programmable only once > after a CPU

[PATCH 1/2] arm64: account for GICv3 LPI tables in static memblock reserve table

2019-02-13 Thread Ard Biesheuvel
In the irqchip and EFI code, we have what basically amounts to a quirk to work around a peculiarity in the GICv3 architecture, which permits the system memory address of LPI tables to be programmable only once after a CPU reset. This means kexec kernels must use the same memory as the first