Re: [PATCH] efi/arm: fix allocation failure when reserving the kernel base

2019-08-20 Thread Russell King - ARM Linux admin
On Fri, Aug 02, 2019 at 05:38:54AM +, Chester Lin wrote:
> diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
> index f3ce34113f89..909b11ba48d8 100644
> --- a/arch/arm/mm/mmu.c
> +++ b/arch/arm/mm/mmu.c
> @@ -1184,6 +1184,9 @@ void __init adjust_lowmem_bounds(void)
>   phys_addr_t block_start = reg->base;
>   phys_addr_t block_end = reg->base + reg->size;
>  
> + if (memblock_is_nomap(reg))
> + continue;
> +
>   if (reg->base < vmalloc_limit) {
>   if (block_end > lowmem_limit)
>   /*

I think this hunk is sane - if the memory is marked nomap, then it isn't
available for the kernel's use, so as far as calculating where the
lowmem/highmem boundary is, it effectively doesn't exist and should be
skipped.

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Re: [PATCH] efi/arm: fix allocation failure when reserving the kernel base

2019-08-20 Thread Russell King - ARM Linux admin
On Sun, Aug 04, 2019 at 10:57:00AM +0300, Ard Biesheuvel wrote:
> (The first TEXT_OFFSET bytes are no longer used in practice, which is
> why putting a reserved region of 4 KB bytes works at the moment, but
> this is fragile).

That is not correct for 32-bit ARM.  The swapper page table is still
located 16kiB below the kernel.

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Re: [PATCH v2] efi/arm: enable CP15 DMB instructions before cleaning the cache

2019-04-12 Thread Russell King - ARM Linux admin
On Fri, Apr 12, 2019 at 02:00:16PM -0700, Ard Biesheuvel wrote:
> If I use the forgotten password feature, it tells me
> 
> """
> The email address you provided (ard.biesheu...@linaro.org) is not
> valid. Please try again.
> """

Fixed, consequence of the upgrades back in January, requiring a
change to the regular expression system, which caused my simple
fixups to then generate an invalid RE.  You should have received
the new password as a result of my testing.

Thanks for reporting the problem - that's the only way problems
get fixed!

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Re: [PATCH v2] efi/arm: enable CP15 DMB instructions before cleaning the cache

2019-04-12 Thread Russell King - ARM Linux admin
On Fri, Apr 12, 2019 at 01:38:12PM -0700, Ard Biesheuvel wrote:
> On Tue, 9 Apr 2019 at 09:42, Ard Biesheuvel  wrote:
> >
> > The EFI stub is entered with the caches and MMU enabled by the
> > firmware, and once the stub is ready to hand over to the decompressor,
> > we clean and disable the caches.
> >
> > The cache clean routines use CP15 barrier instructions, which can be
> > disabled via SCTLR. Normally, when using the provided cache handling
> > routines to enable the caches and MMU, this bit is enabled as well.
> > However, but since we entered the stub with the caches already enabled,
> > this routine is not executed before we call the cache clean routines,
> > resulting in undefined instruction exceptions if the firmware never
> > enabled this bit.
> >
> > So set the bit explicitly in the EFI entry code, but do so in a way that
> > guarantees that the resulting code can still run on v6 cores as well
> > (which are guaranteed to have CP15 barriers enabled)
> >
> > Acked-by: Marc Zyngier 
> > Signed-off-by: Ard Biesheuvel 
> > ---
> >  arch/arm/boot/compressed/head.S | 16 +++-
> >  1 file changed, 15 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/boot/compressed/head.S 
> > b/arch/arm/boot/compressed/head.S
> > index 6c7ccb428c07..c174098acdf1 100644
> > --- a/arch/arm/boot/compressed/head.S
> > +++ b/arch/arm/boot/compressed/head.S
> > @@ -1438,7 +1438,21 @@ ENTRY(efi_stub_entry)
> >
> > @ Preserve return value of efi_entry() in r4
> > mov r4, r0
> > -   bl  cache_clean_flush
> > +
> > +   @ our cache maintenance code relies on CP15 barrier 
> > instructions
> > +   @ but since we arrived here with the MMU and caches 
> > configured
> > +   @ by UEFI, we must check that the CP15BEN bit is set in 
> > SCTLR.
> > +   @ Note that this bit is RAO/WI on v6 and earlier, so the 
> > ISB in
> > +   @ the enable path will be executed on v7+ only.
> > +   mrc p15, 0, r1, c1, c0, 0   @ read SCTLR
> > +   tst r1, #(1 << 5)   @ CP15BEN bit set?
> > +   bne 0f
> > +   orr r1, r1, #(1 << 5)   @ CP15 barrier instructions
> > +   mcr p15, 0, r1, c1, c0, 0   @ write SCTLR
> > + ARM(  .inst   0xf57ff06f  @ isb   )
> > + THUMB(isb )
> > +
> > +0: bl  cache_clean_flush
> > bl  cache_off
> >
> > @ Set parameters for booting zImage according to boot 
> > protocol
> > --
> > 2.17.1
> >
> 
> Russell, do you mind if I take this through the EFI tree?

Yes I do mind.

> I had trouble logging into your patch system (it no longer recognizes my
> email address

I can't debug it based on that - what does it say?

> but when I try to re-create the account, my name is already taken)

Yes, duplicate accounts can't be created, but there is also a forgotten
password feature.

I've just checked and I can log in fine.

-- 
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