On 2/3/2015 5:41 PM, Dmitry Torokhov wrote:
On Tue, Feb 03, 2015 at 05:09:06PM -0800, Ray Jui wrote:
This adds the initial support of the Broadcom Cygnus GPIO/PINCONF driver
that supports all 3 GPIO controllers on Cygnus including the ASIU GPIO
controller, the chipCommonG GPIO controller,
This patchset contains the initial pinctrl (IOMUX) support for the Broadcom
Cygnus SoC. The Cygnus IOMUX controller supports group based mux configuration
and allows certain pins to be muxed to GPIO function individually
Changes from v3:
- Fix the driver to have more proper use of const in
This enables the IOMUX support for Broadcom Cygnus SoC
Signed-off-by: Ray Jui r...@broadcom.com
---
arch/arm/boot/dts/bcm-cygnus.dtsi |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi
b/arch/arm/boot/dts/bcm-cygnus.dtsi
index 5126f9e..b014ce5 100644
At 2015-02-03 21:21:43, Linus Walleij linus.wall...@linaro.org wrote:
On Wed, Jan 28, 2015 at 3:30 AM, Chao Xie chao@marvell.com wrote:
From: Chao Xie chao@marvell.com
For some old PXA series, they used PXA GPIO driver.
The IP of GPIO changes since PXA988 which is Marvell MMP
Device tree binding documentation for Broadcom Cygnus IOMUX driver
Signed-off-by: Ray Jui r...@broadcom.com
Reviewed-by: Scott Branden sbran...@broadcom.com
---
.../bindings/pinctrl/brcm,cygnus-pinmux.txt| 157
1 file changed, 157 insertions(+)
create mode 100644
This adds the initial driver support for the Broadcom Cygnus IOMUX
controller. The Cygnus IOMUX controller supports group based mux
configuration but allows certain pins to be muxed to GPIO individually
Signed-off-by: Ray Jui r...@broadcom.com
Reviewed-by: Scott Branden sbran...@broadcom.com
---
On Sat, Jan 31, 2015 at 02:39:03PM +0100, Alexandre Courbot wrote:
On Sat, Jan 31, 2015 at 9:33 AM, folkert folk...@vanheusden.com wrote:
Michael,
For timekeeping I wrote a program which waits for interrupts on
gpio-pins and then tells the local ntp daemon the clock offset.
I'm aware
From 5b3a2d45214ae263f7ca284291ef3fc2577f19f7 Mon Sep 17 00:00:00 2001
From: Ken Xue ken@amd.com
Date: Tue, 3 Feb 2015 15:42:17 +0800
Subject: [PATCH] pinctrl: add AMD GPIO driver support.
KERNCZ GPIO is a new IP from AMD. it can be implemented in both x86 and ARM.
Current driver patch only
On Fri, Jan 30, 2015 at 12:04:01PM +0200, Stanimir Varbanov wrote:
From: Joonwoo Park joonw...@codeaurora.org
Add initial pinctrl driver to support pin configuration with
pinctrl framework for msm8916.
Signed-off-by: Joonwoo Park joonw...@codeaurora.org
Signed-off-by: Stanimir Varbanov
On Wed, Jan 28, 2015 at 3:30 AM, Chao Xie chao@marvell.com wrote:
From: Chao Xie chao@marvell.com
For some old PXA series, they used PXA GPIO driver.
The IP of GPIO changes since PXA988 which is Marvell MMP
series.
It will use new way to control the GPIO level, direction
and edge
On Tue, Jan 27, 2015 at 5:46 AM, Rob Herring r...@kernel.org wrote:
In preparation to enable ARCH_MMP on ARM64, the include of mach/irqs.h
must be eliminated. mach/irqs.h was being included for IRQ_GPIO{0,1},
but these IRQs are always passed in as resources now. We can use irq0
and irq1 and
On Tue, Jan 27, 2015 at 5:46 AM, Rob Herring r...@kernel.org wrote:
Add support for PXA1928 GPIOs. The PXA1928 adds a 6th bank from previous
generations.
Signed-off-by: Jing Xiang jxi...@marvell.com
Signed-off-by: Xiangzhan Meng meng...@marvell.com
[robh: ported to 3.19 from vendor kernel]
On Fri, Jan 30, 2015 at 11:46 AM, Linus Walleij
linus.wall...@linaro.org wrote:
Take a sweep to bring the irq support for the MAX732x expanders
into the gpiolib core to cut down on duplicated code.
Only compile tested! I need some feedback from people using this
expander with interrupts to
On Tue, Jan 27, 2015 at 5:46 AM, Rob Herring r...@kernel.org wrote:
Add a new compatible string for PXA1928 GPIO controller. The IP block is
same as prior chips with a 6th bank added.
Signed-off-by: Rob Herring r...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland
On Tue, Jan 27, 2015 at 11:50 PM, Uwe Kleine-König
u.kleine-koe...@pengutronix.de wrote:
The right check for conf_reg to be invalid it testing against -1 not 0
as is done in the rest of the driver.
This fixes an oops that can be triggered by:
cat
On Wed, Jan 28, 2015 at 12:45 AM, Uwe Kleine-König
u.kleine-koe...@pengutronix.de wrote:
The pin id for a given tuple listed in a fsl,pins property is calculated
by dividing the first entry (which is also a register offset) by 4.
As the first available register is at offset 0x8 and configures
Hi Ray,
On Mon, Feb 02, 2015 at 06:01:33PM -0800, Ray Jui wrote:
This adds the initial driver support for the Broadcom Cygnus IOMUX
controller. The Cygnus IOMUX controller supports group based mux
configuration but allows certain pins to be muxed to GPIO individually
Signed-off-by: Ray Jui
On 2/3/2015 9:40 AM, Dmitry Torokhov wrote:
Hi Ray,
On Mon, Feb 02, 2015 at 06:01:33PM -0800, Ray Jui wrote:
This adds the initial driver support for the Broadcom Cygnus IOMUX
controller. The Cygnus IOMUX controller supports group based mux
configuration but allows certain pins to be
On Tue, Feb 03, 2015 at 11:29:36AM -0800, Ray Jui wrote:
On 2/3/2015 9:40 AM, Dmitry Torokhov wrote:
On Mon, Feb 02, 2015 at 06:01:33PM -0800, Ray Jui wrote:
+
+/*
+ * List of pins in Cygnus
+ */
+static struct cygnus_pin cygnus_pins[] = {
const?
I cannot make it const here,
On Tue, Feb 03, 2015 at 02:01:09PM +0100, Linus Walleij wrote:
On Tue, Jan 27, 2015 at 11:50 PM, Uwe Kleine-König
u.kleine-koe...@pengutronix.de wrote:
The right check for conf_reg to be invalid it testing against -1 not 0
as is done in the rest of the driver.
This fixes an oops that
On 2/3/2015 12:00 PM, Dmitry Torokhov wrote:
On Tue, Feb 03, 2015 at 11:29:36AM -0800, Ray Jui wrote:
On 2/3/2015 9:40 AM, Dmitry Torokhov wrote:
On Mon, Feb 02, 2015 at 06:01:33PM -0800, Ray Jui wrote:
+
+/*
+ * List of pins in Cygnus
+ */
+static struct cygnus_pin cygnus_pins[] = {
Make of_device_id array const.
Signed-off-by: Sanjeev Sharma sanjeev_sha...@mentor.com
---
drivers/pinctrl/freescale/pinctrl-vf610.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c
b/drivers/pinctrl/freescale/pinctrl-vf610.c
index
This adds the initial support of the Broadcom Cygnus GPIO/PINCONF driver
that supports all 3 GPIO controllers on Cygnus including the ASIU GPIO
controller, the chipCommonG GPIO controller, and the always-on GPIO
controller. Basic PINCONF configurations such as bias pull up/down, and
drive strength
This enables all 3 GPIO controllers including the ASIU GPIO, the
chipcommonG GPIO, and the ALWAYS-ON GPIO, for Broadcom Cygnus SoC
Signed-off-by: Ray Jui r...@broadcom.com
Reviewed-by: Scott Branden sbran...@broadcom.com
---
arch/arm/boot/dts/bcm-cygnus.dtsi | 33
Document the GPIO/PINCONF device tree binding for Broadcom Cygnus SoC
Signed-off-by: Ray Jui r...@broadcom.com
Reviewed-by: Scott Branden sbran...@broadcom.com
---
.../bindings/pinctrl/brcm,cygnus-gpio.txt | 102
1 file changed, 102 insertions(+)
create mode
This enables GPIO based phone hook detection for Broadcom BCM911360
phone factor board (bcm911360_entphn)
Signed-off-by: Ray Jui r...@broadcom.com
---
arch/arm/boot/dts/bcm911360_entphn.dts | 13 +
1 file changed, 13 insertions(+)
diff --git
This patchset contains the initial GPIO/PINCONF support for the Broadcom
Cygnus SoC.
Cygnus has 3 GPIO controllers: 1) the ASIU GPIO; 2) the chipCommonG GPIO;
and 3) the ALWAYS-ON GPIO. All 3 types of GPIO controllers are supported by
the this driver.
All 3 Cygnus GPIO controllers support basic
On Tue, Feb 03, 2015 at 05:09:06PM -0800, Ray Jui wrote:
This adds the initial support of the Broadcom Cygnus GPIO/PINCONF driver
that supports all 3 GPIO controllers on Cygnus including the ASIU GPIO
controller, the chipCommonG GPIO controller, and the always-on GPIO
controller. Basic PINCONF
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