On Mon, Mar 09, 2015 at 01:12:03PM +0200, Mika Westerberg wrote:
On Fri, Mar 06, 2015 at 11:08:38PM +0800, qipeng.zha wrote:
From: qipeng.zha qipeng@intel.com
If GPIO driver use pin mapping, need to tranlate pin number
typo, should
On Fri, Mar 06, 2015 at 11:08:38PM +0800, qipeng.zha wrote:
From: qipeng.zha qipeng@intel.com
If GPIO driver use pin mapping, need to tranlate pin number
typo, should be translate
between ACPI table and GPIO driver.
This issue is
On Mon, Mar 2, 2015 at 10:30 PM, Rob Herring r...@kernel.org wrote:
The macro BANK_OFF which calculates the base offset for each GPIO port.
The macro is needlessly complex and unreadable. Simplify the
calculation to a simple math operation.
Signed-off-by: Rob Herring r...@kernel.org
Cc:
On Tue, Mar 3, 2015 at 9:47 AM, Alexey Brodkin
alexey.brod...@synopsys.com wrote:
It's possible that boot-loader that worked on CPU before Linux kernel
made some changes in GPIO controller registers. For example interrupts
could be all masked.
Current implementation of DW GPIO driver relies
Geert Uytterhoeven ge...@linux-m68k.org writes:
Hi Pavel,
On Sun, Mar 8, 2015 at 9:57 PM, Pavel Machek pa...@ucw.cz wrote:
Ok, so I played with RGB LED a bit, and we have quite a gap in
documentation: what 50% brightness means is non-trivial and very
important in case we want to do smooth
On Mon, Mar 2, 2015 at 3:55 PM, Baruch Siach bar...@tkos.co.il wrote:
struct pinctrl_desc does not contain the maxpin member since commit 0d2006bbf0
(pinctrl: remove unnecessary max pin number).
Fixes: 0d2006bbf0 ('pinctrl: remove unnecessary max pin number')
Signed-off-by: Baruch Siach
On Mon, Mar 9, 2015 at 6:21 AM, Alexandre Courbot gnu...@gmail.com wrote:
Hi,
On Mon, Mar 9, 2015 at 5:14 AM, Lucas De Marchi
lucas.de.mar...@gmail.com wrote:
I was looking at drivers/leds/ in how it interacts with gpiolib. I see
that there's a new gpiod_* API.
git grep gpio_request --
On Fri, Feb 20, 2015 at 7:01 PM, Maxime Coquelin
mcoquelin.st...@gmail.com wrote:
This patch adds clocksource support for ARMv7-M's System timer,
also known as SysTick.
Signed-off-by: Maxime Coquelin mcoquelin.st...@gmail.com
(...)
+ /* If no clock found, try to get clock-frequency
On Wed, Mar 4, 2015 at 1:43 PM, Alexandre Courbot gnu...@gmail.com wrote:
On Tue, Mar 3, 2015 at 7:31 PM, Linus Walleij linus.wall...@linaro.org
wrote:
On Tue, Mar 3, 2015 at 9:27 AM, Alexandre Courbot gnu...@gmail.com wrote:
It really comes down to how user-space wants to access GPIOs. I
On 03/07/2015 01:10 PM, Linus Walleij wrote:
On Tue, Feb 24, 2015 at 10:00 PM, Stephen Warren swar...@wwwdotorg.org wrote:
From: Stephen Warren swar...@nvidia.com
Both nvidia,io-hv and nvidia,rcv-sel represent the fact that a particular
pin's IO buffers are configured to accept high voltage
On Wed, Mar 4, 2015 at 7:53 AM, Ken Xue ken@amd.com wrote:
From c2258b4b550d8f61a5eb64fee25d4c0fdd3a1e91 Mon Sep 17 00:00:00 2001
From: Ken Xue ken@amd.com
Date: Wed, 4 Mar 2015 14:48:36 +0800
Subject: [PATCH] pinctrl: add AMD GPIO driver support.
KERNCZ GPIO is a new IP from AMD.
On Thu, Feb 26, 2015 at 8:41 AM, Sonic Zhang sonic@gmail.com wrote:
From: Sonic Zhang sonic.zh...@analog.com
The blackfin pinmux and gpio controller doesn't allow user to set up 1 pin
for both GPIO and peripheral function. So, check both gpio_owner and
mux_owner before approving the pin
On Mon, Mar 2, 2015 at 6:28 PM, Baruch Siach bar...@tkos.co.il wrote:
There is no code ender the 'err' label. Just return the error code directly.
Signed-off-by: Baruch Siach bar...@tkos.co.il
Patch applied with the ACKs.
Yours,
Linus Walleij
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On Wed, Mar 4, 2015 at 11:41 AM, Stanimir Varbanov svarba...@mm-sol.com wrote:
This makes the pinctrl driver to use the generic pinconf
interface. Mainly it gives us a way to use debugfs to dump
group configurations.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
Reviewed-by: Linus
On Fri, Feb 6, 2015 at 5:30 PM, Stefan Agner ste...@agner.ch wrote:
Commit 3dac1918a491 (pinctrl: imx: detect uninitialized pins) needs
the values in struct imx_pin_reg to be -1. This has been done in a
rather unorthodox way by setting the memory to 0xff using memset...
Use a proper for loop
On Thu, Mar 5, 2015 at 12:23 AM, Stefan Agner ste...@agner.ch wrote:
Do you generally agree to that change?
@Linus Walleij, anything holding this patch back from getting merged?
Nothing apart from me being overloaded.
Merged now, thanks.
Yours,
Linus Walleij
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On Thu, Mar 5, 2015 at 1:35 AM, Ray Jui r...@broadcom.com wrote:
Device tree binding documentation for Broadcom Cygnus IOMUX driver
Signed-off-by: Ray Jui r...@broadcom.com
Reviewed-by: Scott Branden sbran...@broadcom.com
Uncontroversial, using standard bindings, so patch applied.
Yours,
On Thu, Mar 5, 2015 at 1:35 AM, Ray Jui r...@broadcom.com wrote:
Consolidate Broadcom pinctrl drivers into drivers/pinctrl/bcm/*
Signed-off-by: Ray Jui r...@broadcom.com
Patch applied.
Yours,
Linus Walleij
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2015-03-09 15:39 GMT+01:00 Linus Walleij linus.wall...@linaro.org:
On Fri, Feb 20, 2015 at 7:01 PM, Maxime Coquelin
mcoquelin.st...@gmail.com wrote:
The STMicrolectornics's STM32F419 MCU has the following main features:
- Cortex-M4 core running up to @180MHz
- 2MB internal flash, 256KBytes
2015-03-09 16:50 GMT+01:00 Linus Walleij linus.wall...@linaro.org:
On Fri, Feb 20, 2015 at 7:01 PM, Maxime Coquelin
mcoquelin.st...@gmail.com wrote:
This patch adds clocksource support for ARMv7-M's System timer,
also known as SysTick.
Signed-off-by: Maxime Coquelin
On Fri, Mar 6, 2015 at 10:55 AM, Maxime Coquelin
mcoquelin.st...@gmail.com wrote:
2015-03-06 10:03 GMT+01:00 Linus Walleij linus.wall...@linaro.org:
On Thu, Feb 12, 2015 at 6:46 PM, Maxime Coquelin
mcoquelin.st...@gmail.com wrote:
Add a MAINTAINER entry covering all STM32 machine and drivers
On Thu, Mar 5, 2015 at 2:36 PM, Rojhalat Ibrahim i...@rtschenk.de wrote:
Extend the documentation for the gpiod_set_array() functions and elaborate
a bit on possible use cases.
Signed-off-by: Rojhalat Ibrahim i...@rtschenk.de
Patch applied. Thanks!
Yours,
Linus Walleij
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On Thu, Mar 5, 2015 at 1:35 AM, Ray Jui r...@broadcom.com wrote:
Document the GPIO/PINCONF device tree binding for Broadcom Cygnus SoC
Signed-off-by: Ray Jui r...@broadcom.com
Reviewed-by: Scott Branden sbran...@broadcom.com
(...)
+- ngpios:
+Total number of GPIOs the controller
On Thu, Mar 5, 2015 at 1:35 AM, Ray Jui r...@broadcom.com wrote:
This adds the initial driver support for the Broadcom Cygnus IOMUX
controller. The Cygnus IOMUX controller supports group based mux
configuration but allows certain pins to be muxed to GPIO individually
Signed-off-by: Ray Jui
On Thu, Mar 5, 2015 at 1:35 AM, Ray Jui r...@broadcom.com wrote:
This enables the IOMUX support for Broadcom Cygnus SoC
Signed-off-by: Ray Jui r...@broadcom.com
Tested-by: Dmitry Torokhov d...@chromium.org
Acked-by: Linus Walleij linus.wall...@linaro.org
Please merge this through the
On Thu, Mar 5, 2015 at 9:03 AM, Paul Bolle pebo...@tiscali.nl wrote:
[...]
+MODULE_AUTHOR(Ray Jui r...@broadcom.com);
+MODULE_DESCRIPTION(Broadcom Cygnus IOMUX driver);
+MODULE_LICENSE(GPL v2);
These three macros will be preprocessed away. (And I guess you could
also drop the linux/module.h
On Fri, Feb 27, 2015 at 6:38 PM, Geert Uytterhoeven
geert+rene...@glider.be wrote:
As PFC registers are either 8, 16, or 32 bits wide, use u32 (mostly
replacing unsigned long) to store (parts of) register values and masks.
Switch the shadow register operations from {set,clear}_bit() to plain
2015-03-09 17:47 GMT+01:00 Linus Walleij linus.wall...@linaro.org:
On Fri, Mar 6, 2015 at 10:55 AM, Maxime Coquelin
mcoquelin.st...@gmail.com wrote:
2015-03-06 10:03 GMT+01:00 Linus Walleij linus.wall...@linaro.org:
On Thu, Feb 12, 2015 at 6:46 PM, Maxime Coquelin
mcoquelin.st...@gmail.com
On Fri, Mar 6, 2015 at 9:59 AM, Uwe Kleine-König
u.kleine-koe...@pengutronix.de wrote:
On Fri, Mar 06, 2015 at 09:26:26AM +0100, Linus Walleij wrote:
On Thu, Feb 12, 2015 at 10:03 AM, Uwe Kleine-König
u.kleine-koe...@pengutronix.de wrote:
I wonder if gpiod_get_optional et all should be
On Fri, Mar 6, 2015 at 11:58 AM, Laurent Pinchart
laurent.pinch...@ideasonboard.com wrote:
Hi Linus,
On Friday 06 March 2015 11:43:45 Linus Walleij wrote:
On Sat, Feb 28, 2015 at 12:39 AM, Sergei Shtylyov wrote:
The pin array handled by sh_pfc_map_pins() may contain holes representing
2015-03-09 1:29 GMT+01:00 Stefan Agner ste...@agner.ch:
On 2015-02-20 19:01, Maxime Coquelin wrote:
From Cortex-M reference manuals, the nvic supports up to 240 interrupts.
So the number of entries in vectors table is up to 256.
This patch adds a new config flag to specify the number of
Hi Linus,
On Mon, Mar 9, 2015 at 5:37 PM, Linus Walleij linus.wall...@linaro.org wrote:
On Fri, Feb 27, 2015 at 6:38 PM, Geert Uytterhoeven
geert+rene...@glider.be wrote:
As PFC registers are either 8, 16, or 32 bits wide, use u32 (mostly
replacing unsigned long) to store (parts of) register
On Thu, Mar 5, 2015 at 6:13 PM, Ray Jui r...@broadcom.com wrote:
(I knew the other three MODULE_* macros are handled in slightly more
complicated way, but the effect is basically that they are preprocessed
away.)
Paul Bolle
Even these module macros will be pre-processed away when the
Hi Linus,
On 3/9/2015 9:30 AM, Linus Walleij wrote:
On Thu, Mar 5, 2015 at 1:35 AM, Ray Jui r...@broadcom.com wrote:
Document the GPIO/PINCONF device tree binding for Broadcom Cygnus SoC
Signed-off-by: Ray Jui r...@broadcom.com
Reviewed-by: Scott Branden sbran...@broadcom.com
(...)
+-
On Fri, Mar 6, 2015 at 12:26 PM, Jonas Gorski j...@openwrt.org wrote:
As far as I understand the second paragraph, it should suffice to
define functions named gpio0, gpio1, etc. instead of adding a
gpio_request_enable().
But I fail to see in pinctrl_request_gpio() where this happens:
On Sun, Feb 8, 2015 at 7:23 PM, Boris Brezillon
boris.brezil...@free-electrons.com wrote:
The gpiochip_lock_as_irq call can fail and return an error, while the
irq_startup is not expected to fail (returns an unsigned int which is not
checked by irq core code).
irq_request/release_resources
Ray Jui schreef op ma 09-03-2015 om 12:00 [-0700]:
I think it depends on how you see it. Based on this logic, then one can
also argue comments in the code will be pre-processed away and are not
needed. They at least serve the same documentation purpose in a way.
So why not make them comments?
Consolidate Broadcom pinctrl drivers into drivers/pinctrl/bcm/*
Signed-off-by: Ray Jui r...@broadcom.com
---
drivers/pinctrl/Kconfig | 19 +--
drivers/pinctrl/Makefile |3 +--
drivers/pinctrl/bcm/Kconfig | 21
This patchset contains the pinmux (IOMUX) and GPIO/PINCONF support for
Broadcom Cygnus SoC.
The Cygnus IOMUX controller supports group based mux
configuration and allows certain pins to be muxed to GPIO function
individually. The IOMUX controller is supported by the pinctrl-cygnus-mux.c
driver.
The company is called Fintek, not Fintech. Fix it.
Signed-off-by: Andreas Bofjall andr...@gazonk.org
Reviewed-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpio/gpio-f7188x.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-f7188x.c
On Friday 06 March 2015 14:24:51 Yingjoe Chen wrote:
Linus,
This one make PINCTRL_MT8173 option user selectable and is based on
mtk-staging in your tree. If you think this is OK, please applied or
squash this into previous change. Thanks.
The patch looks good in principle, just two small
This adds the initial support of the Broadcom Cygnus GPIO/PINCONF driver
that supports all 3 GPIO controllers on Cygnus including the ASIU GPIO
controller, the chipCommonG GPIO controller, and the always-on GPIO
controller. Basic PINCONF configurations such as bias pull up/down, and
drive strength
Device tree binding documentation for Broadcom Cygnus IOMUX driver
Signed-off-by: Ray Jui r...@broadcom.com
Reviewed-by: Scott Branden sbran...@broadcom.com
---
.../bindings/pinctrl/brcm,cygnus-pinmux.txt| 132
1 file changed, 132 insertions(+)
create mode 100644
This enables GPIO based phone hook detection for Broadcom BCM911360
phone factor board (bcm911360_entphn)
Signed-off-by: Ray Jui r...@broadcom.com
---
arch/arm/boot/dts/bcm911360_entphn.dts | 13 +
1 file changed, 13 insertions(+)
diff --git
This enables the IOMUX support for Broadcom Cygnus SoC
Signed-off-by: Ray Jui r...@broadcom.com
Tested-by: Dmitry Torokhov d...@chromium.org
---
arch/arm/boot/dts/bcm-cygnus.dtsi |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi
Document the GPIO/PINCONF device tree binding for Broadcom Cygnus SoC
Signed-off-by: Ray Jui r...@broadcom.com
Reviewed-by: Scott Branden sbran...@broadcom.com
---
.../bindings/pinctrl/brcm,cygnus-gpio.txt | 98
1 file changed, 98 insertions(+)
create mode 100644
On Wed, 2015-03-04 at 13:08 +0100, Maxime Coquelin wrote:
This is because I added also support for COMPILE_TEST coverage as per
Uwe advice,
and thought it was necessary to have an entry for this.
Maybe I'm just wrong?
I missed that you added COMPILE_TEST.
A quick scan of your idea doesn't
Add support for the GPIOs found on the Fintek SuperI/O chip F71869, such
as the one found on the Jetway NF96u-525 motherboard, to the f7188x gpio
driver.
Signed-off-by: Andreas Bofjall andr...@gazonk.org
Tested-by: Les Schaffer schaf...@optonline.net
Reviewed-by: Alexandre Courbot
Add support for the GPIOs found on the Fintek SuperI/O chip F71869A,
such as the one found on the Jetway JNF99-525 motherboard, to the f7188x
gpio driver.
Signed-off-by: Andreas Bofjall andr...@gazonk.org
Reviewed-by: Alexandre Courbot acour...@nvidia.com
---
drivers/gpio/Kconfig | 4 ++--
Hi,
this series adds support for the gpio pins on the Fintek F71869 and F71869A
SuperI/O chips to the gpio-f7188x driver. The chips are used on for example
Jetway motherboards.
The driver has been tested on two different boards: a JNF99-525 with F71869A,
and by Les Schaffer on a Jetway NF96u-525
Linus Walleij schreef op ma 09-03-2015 om 17:41 [+0100]:
As pointed out in another mail on similar subject, I think these macros
are a kind of obsolete documentation and if they should be dropped we
need to go over an entire subsystem at a time and remove all boolean users
in a big patch.
Whoever comes up with a cleaner sysfs or a clean device interface
will win the argument and lock the path for the other approach.
It's like a forking path with no going back or something.
Can't we just do it a bit like v4l2 does it?
E.g. an open /dev/gpio and then an ioctl which queries all
Ray Jui schreef op ma 09-03-2015 om 12:40 [-0700]:
I don't see this as an issue to be quite honest.
(Off topic: is issue a, well, strong word? To my (non-English) mind it's
rather neutral, carrying by itself less urgency than, say, problem. If
I'm wrong I might have confused quite a few people
Linus Walleij schreef op ma 09-03-2015 om 17:28 [+0100]:
I think you're right. Or I fear you're right.
But this problem is present in so many drivers that a generic
fixup needs to be done with a script and across an entire subsystem
at once,
Why don't we start with checking for similar
Signed-off-by: Baruch Siach bar...@tkos.co.il
---
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
On Mon, Mar 09, 2015 at 04:52:26PM +0100, Linus Walleij wrote:
On Wed, Mar 4, 2015 at 1:43 PM, Alexandre Courbot gnu...@gmail.com wrote:
On Tue, Mar 3, 2015 at 7:31 PM, Linus Walleij linus.wall...@linaro.org
wrote:
On Tue, Mar 3, 2015 at 9:27 AM, Alexandre Courbot gnu...@gmail.com wrote:
Hello,
On Mon, Mar 09, 2015 at 10:12:32PM +0100, Paul Bolle wrote:
On Wed, 2015-03-04 at 13:08 +0100, Maxime Coquelin wrote:
This is because I added also support for COMPILE_TEST coverage as per
Uwe advice,
and thought it was necessary to have an entry for this.
Maybe I'm just wrong?
On Mon, Mar 2, 2015 at 8:23 AM, Kefeng Wang wangkefeng.w...@huawei.com wrote:
Hisilicon arm64 soc uses designWare gpio, re-enable it after
commit 1972c97db5b(gpio: dwapb: fix compile errors).
Signed-off-by: Kefeng Wang wangkefeng.w...@huawei.com
Patch applied. I cannot see patch 1/2 I guess
On Fri, 2015-03-06 at 12:05 +0100, Paul Bolle wrote:
On Fri, 2015-03-06 at 14:24 +0800, Yingjoe Chen wrote:
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -8,11 +8,13 @@ config PINCTRL_MTK_COMMON
select OF_GPIO
config PINCTRL_MT8135
-
On Fri, Feb 27, 2015 at 09:47:17AM -0800, David Cohen wrote:
Hi Mika,
On Thu, Feb 26, 2015 at 09:11:09AM +0200, Westerberg, Mika wrote:
On Thu, Feb 26, 2015 at 05:10:13AM +0200, Zha, Qipeng wrote:
Hi
Please check below patch(or attached), thanks.
this is verified on
Change based on Paul's suggestion.
Old patch can be found at:
http://lists.infradead.org/pipermail/linux-mediatek/2015-March/57.html
--
ARM64 maintainer doesn't want to add MACH_* for each SoC.
Adjust mt8173 pinctrl kconfig entry so user can manually select it.
Also make PINCTRL_MT8135
On Mon 2015-03-09 09:08:37, Geert Uytterhoeven wrote:
Hi Pavel,
On Sun, Mar 8, 2015 at 9:57 PM, Pavel Machek pa...@ucw.cz wrote:
Ok, so I played with RGB LED a bit, and we have quite a gap in
documentation: what 50% brightness means is non-trivial and very
important in case we want to do
Hi,
On Mon, Mar 9, 2015 at 5:14 AM, Lucas De Marchi
lucas.de.mar...@gmail.com wrote:
I was looking at drivers/leds/ in how it interacts with gpiolib. I see
that there's a new gpiod_* API.
git grep gpio_request -- drivers/leds/ reveals quite a number of
users of gpio_request() and
On Sat, Feb 28, 2015 at 9:46 PM, Colin King colin.k...@canonical.com wrote:
From: Colin Ian King colin.k...@canonical.com
Fix typo, flaged - flagged
Signed-off-by: Colin Ian King colin.k...@canonical.com
Patch applied.
Yours,
Linus Walleij
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On Thu, Feb 26, 2015 at 10:36 AM, Alexandre Courbot gnu...@gmail.com wrote:
On Mon, Jan 26, 2015 at 2:16 AM, Andreas Bofjall andr...@gazonk.org wrote:
Hi,
this series adds support for the gpio pins on the Fintek F71869 and F71869A
SuperI/O chips to the gpio-f7188x driver. The chips are used
On Mon, 9 Mar 2015, Linus Walleij wrote:
On Thu, Feb 26, 2015 at 10:36 AM, Alexandre Courbot gnu...@gmail.com wrote:
On Mon, Jan 26, 2015 at 2:16 AM, Andreas Bofjall andr...@gazonk.org wrote:
Hi,
this series adds support for the gpio pins on the Fintek F71869 and F71869A
SuperI/O chips to
On Tue, Mar 03, 2015 at 06:13:22PM +0800, qipeng.zha wrote:
From: qipeng.zha qipeng@intel.com
From the comments of gpiod_direction_output(), need to set @value
as initial output, so update the lowlevel routine to make it work.
Signed-off-by: jason.cj.chenjason.cj.c...@intel.com
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