From: Laurent Pinchart laurent.pinchart+rene...@ideasonboard.com
GPIO banks 1 and 2 are missing pins 30 and 31. Remove them.
Signed-off-by: Laurent Pinchart laurent.pinchart+rene...@ideasonboard.com
Signed-off-by: Sergei Shtylyov sergei.shtyl...@cogentembedded.com
---
Changes in version 2:
-
Oops, the subject should have been [PATCH v2 0/4] Remove non-existing
GPIO pins for R8A7790/1.
WBR, Sergei
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Hi Y,
On Thu, Jun 04, 2015 at 02:25:12PM +0700, Y Vo wrote:
GIC is designed to support two of trigger mechanisms - active level
high or edge rising. But in the gpio_keys driver, it tries to use both
edge rising and edge falling trigger. This patch fixes the gpio_keys
driver to request only the
Hello.
There was no procedure by which a read only register is initialized
in bgpio_init, so it was added.
Signed-off-by: Yoshinori Sato ys...@users.sourceforge.jp
---
drivers/gpio/gpio-74xx-mmio.c | 2 +-
drivers/gpio/gpio-clps711x.c| 4 ++--
drivers/gpio/gpio-dwapb.c | 2 +-
On 06/04/2015 11:39 AM, Tomeu Vizoso wrote:
On 3 June 2015 at 21:57, grygorii.stras...@linaro.org
grygorii.stras...@linaro.org wrote:
On 05/28/2015 07:33 AM, Rob Herring wrote:
On Mon, May 25, 2015 at 9:53 AM, Tomeu Vizoso tomeu.viz...@collabora.com
wrote:
I have a problem with the panel on
Hello Jiang,
On Thu, Jun 4, 2015 at 6:13 AM, Jiang Liu jiang@linux.intel.com wrote:
Now most IRQ flow handlers make no use of the first parameter 'irq'.
And for those who do make use of 'irq', we could easily get the irq
number through irq_desc-irq_data-irq. So kill the first parameter
Add standby domain gpio controller for APM X-Gene SoC platform.
Signed-off-by: Y Vo y...@apm.com
---
arch/arm64/boot/dts/apm/apm-storm.dtsi | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
On 27 May 2015 at 13:34, Chaotian Jing chaotian.j...@mediatek.com wrote:
On Tue, 2015-05-26 at 14:33 +0200, Ulf Hansson wrote:
[...]
+{
+ unsigned long tmo = jiffies + msecs_to_jiffies(20);
+
+ while ((readl(host-base + SDC_STS) SDC_STS_CMDBUSY)
+
Hello Jiang,
On Thu, Jun 4, 2015 at 6:13 AM, Jiang Liu jiang@linux.intel.com wrote:
Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc while we
already have a pointer to corresponding irq_desc.
Signed-off-by: Jiang Liu jiang@linux.intel.com
Acked-by: Linus Walleij
GIC is designed to support two of trigger mechanisms - active level
high or edge rising. But in the gpio_keys driver, it tries to use both
edge rising and edge falling trigger. This patch fixes the gpio_keys
driver to request only the edge rising event when failed to configure the
interrupt.
On Thu, Jun 04, 2015 at 10:19:24AM +0100, Mark Brown wrote:
On Thu, Jun 04, 2015 at 10:30:10AM +0200, Linus Walleij wrote:
+#define WM8903_GPn_PU_MASK 0x0004 /* GPn_PU */
+#define WM8903_GPn_PU_SHIFT 2 /* GPn_PU */
+#define
On Thu, Jun 04, 2015 at 10:24:39AM +0100, Charles Keepax wrote:
On Thu, Jun 04, 2015 at 10:19:24AM +0100, Mark Brown wrote:
There's that as well, but more generally I'm not sure if there's even
any use of those defines for the driver (without looking at the source
to check).
Many of the
On 3 June 2015 at 21:57, grygorii.stras...@linaro.org
grygorii.stras...@linaro.org wrote:
Hi Tomeu,
On 05/28/2015 07:33 AM, Rob Herring wrote:
On Mon, May 25, 2015 at 9:53 AM, Tomeu Vizoso tomeu.viz...@collabora.com
wrote:
I have a problem with the panel on my Tegra Chromebook taking longer
On Mon, Jun 1, 2015 at 2:53 PM, Fabio Estevam
fabio.este...@freescale.com wrote:
platform_driver does not need to set the owner field, as it will be
populated by the driver core, so just remove it.
The semantic patch that makes this change is available
in
On Mon, Jun 1, 2015 at 2:57 PM, Fabio Estevam
fabio.este...@freescale.com wrote:
PTR_ERR should access the value just tested by IS_ERR
The semantic patch that makes this change is available
in scripts/coccinelle/tests/odd_ptr_err.cocci.
Signed-off-by: Fabio Estevam
On Thu, Jun 04, 2015 at 10:30:10AM +0200, Linus Walleij wrote:
On Tue, Jun 2, 2015 at 1:09 AM, Vladimir Zapolskiy v...@mleia.com wrote:
All GPIO1/2/3/4/5 control registers have the same bit map, but in
implementation of gpiolib callbacks WM8903_GPn_*, WM8903_GP1_* and
WM8903_GP2_* macro
On Tue, Jun 2, 2015 at 11:38 AM, Rojhalat Ibrahim i...@rtschenk.de wrote:
Patch gpiolib: rename gpiod_set_array to gpiod_set_array_value omitted
to also change the function names in the documentation. Let's fix that.
Signed-off-by: Rojhalat Ibrahim i...@rtschenk.de
Patch applied.
Yours,
On Thu, Jun 04, 2015 at 10:54:03AM +0800, Chaotian Jing wrote:
On Tue, 2015-05-19 at 13:15 +0200, Sascha Hauer wrote:
On Tue, May 19, 2015 at 02:36:46PM +0800, Chaotian Jing wrote:
Add Mediatek MMC driver code
Support eMMC/SD/SDIO
Signed-off-by: Chaotian Jing
On Mon, Jun 1, 2015 at 2:00 PM, Anurag Kumar Vulisha
anurag.kumar.vuli...@xilinx.com wrote:
Added support to ZynqMP SoC on the existing zynq gpio driver.
Signed-off-by: Anurag Kumar Vulisha anura...@xilinx.com
+static const struct of_device_id zynq_gpio_of_match[] = {
+ { .compatible
On Tue, Jun 2, 2015 at 1:09 AM, Vladimir Zapolskiy v...@mleia.com wrote:
All GPIO1/2/3/4/5 control registers have the same bit map, but in
implementation of gpiolib callbacks WM8903_GPn_*, WM8903_GP1_* and
WM8903_GP2_* macro are mixed up. Replace particular GPIOn control
register bit
On Thu, Jun 04, 2015 at 10:30:10AM +0200, Linus Walleij wrote:
+#define WM8903_GPn_PU_MASK 0x0004 /* GPn_PU */
+#define WM8903_GPn_PU_SHIFT 2 /* GPn_PU */
+#define WM8903_GPn_PU_WIDTH 1 /* GPn_PU */
Hi Linus,
-Original Message-
From: Linus Walleij [mailto:linus.wall...@linaro.org]
Sent: Thursday, June 04, 2015 1:38 PM
To: Anurag Kumar Vulisha
Cc: Alexandre Courbot; Michal Simek; Soren Brinkmann; linux-
g...@vger.kernel.org; linux-ker...@vger.kernel.org; linux-arm-
On Thu, Jun 4, 2015 at 6:13 AM, Jiang Liu jiang@linux.intel.com wrote:
Change irq flow handlers to prepare for killing the first parameter 'irq'
of irq_flow_handler_t.
Signed-off-by: Jiang Liu jiang@linux.intel.com
Acked-by: Linus Walleij linus.wall...@linaro.org
Yours,
Linus
Added support to Zynq Ultrascale+ MPSoC on the existing zynq gpio driver.
Signed-off-by: Anurag Kumar Vulisha anura...@xilinx.com
---
Chnages in v2:
1.Added device tree bingings for Zynq Ultrascale+ MPSoC
2.Changed the commit message and subject from ZynqMP to
Zynq
On Thu, Jun 4, 2015 at 6:13 AM, Jiang Liu jiang@linux.intel.com wrote:
Now most IRQ flow handlers make no use of the first parameter 'irq'.
And for those who do make use of 'irq', we could easily get the irq
number through irq_desc-irq_data-irq. So kill the first parameter
'irq' of
On 06/04/2015 02:10 PM, Anurag Kumar Vulisha wrote:
Added support to Zynq Ultrascale+ MPSoC on the existing zynq gpio driver.
Signed-off-by: Anurag Kumar Vulisha anura...@xilinx.com
---
Chnages in v2:
1.Added device tree bingings for Zynq Ultrascale+ MPSoC
2.Changed the commit
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