merges hwmon-next. next-20190416 is missing one patch which touches
Documentation/hwmon, but that should be easy to deal with.
Thanks,
Guenter
Guenter Roeck writes:
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>
> Alphabetic include file order please.
Sure
>> +
>> +static struct pmbus_driver_info ir3570b_info = {
>> +.pages = 1,
>
> Either this ...
>
>> +.format[PSC_VOLTAGE_IN] = linear,
>> +
Em Tue, 16 Apr 2019 13:31:14 -0700
Guenter Roeck escreveu:
> On Tue, Apr 16, 2019 at 02:19:49PM -0600, Jonathan Corbet wrote:
> > On Fri, 12 Apr 2019 20:09:16 -0700
> > Guenter Roeck wrote:
> >
> > > The big real-world question is: Is the series good enough for you to
> > > accept,
> > > or
Hi Guenter,
Thanks for taking the time to review these patches. Please see my
comments inline.
Guenter Roeck writes:
> On Tue, Apr 16, 2019 at 11:36:16AM -0700, Ruslan Babayev wrote:
>> +static ssize_t pmbus_show_operation(struct device *dev,
>> +struct
The CONFIG register has two 3-bit fields for conversion time
settings of Bus-voltage and Shunt-voltage, respectively. The
conversion settings, along with averaging mode, allow users
to optimize available timing requirement.
This patch adds an 'update_interval' sysfs node through the
On Tue, Apr 16, 2019 at 03:43:50PM +, Eddie James wrote:
> From: Eddie James
>
> The help text needs to spell out how the driver runs on a BMC, as it
> previously seemed to indicate it ran on a POWER processor.
>
> Signed-off-by: Eddie James
Applied.
Thanks,
Guenter
> ---
>
On Tue, Apr 16, 2019 at 03:43:49PM +, Eddie James wrote:
> The error sysfs attribute returns the stored error state of the OCC and
> doesn't depend on the OCC poll response. Therefore, split the error
> attribute into it's own function to avoid failing out of the function if
> the poll
On Tue, Apr 16, 2019 at 03:43:48PM +, Eddie James wrote:
> The OCC driver limits the rate of sending poll commands to the OCC. If a
> user reads a hwmon entry after a poll response resulted in an error and
> is rate-limited, the error is invisible to the user. Fix this by storing
> the last
On Tue, Apr 16, 2019 at 11:36:19AM -0700, Ruslan Babayev wrote:
> TPS40422 has MFR_SPECIFIC registers STEP_VREF_MARGIN_HIGH and
> STEP_VREF_MARGIN_LOW, which are signed 16-bit in units of 2mV. This
> value is an offset from the nominal reference voltage of 600mV.
>
> For instance, the default
On Tue, Apr 16, 2019 at 12:40:33PM -0700, Guenter Roeck wrote:
> On Tue, Apr 16, 2019 at 11:36:17AM -0700, Ruslan Babayev wrote:
> > On some devices (like IR35215) READ_VIN and READ_IIN registers are
> > paged.
> >
> > For devices where these registers are not paged the extra check
> > ensures we
On Tue, Apr 16, 2019 at 02:19:49PM -0600, Jonathan Corbet wrote:
> On Fri, 12 Apr 2019 20:09:16 -0700
> Guenter Roeck wrote:
>
> > The big real-world question is: Is the series good enough for you to accept,
> > or do you expect some level of user/kernel separation ?
>
> I guess it can go in;
On Fri, 12 Apr 2019 20:09:16 -0700
Guenter Roeck wrote:
> The big real-world question is: Is the series good enough for you to accept,
> or do you expect some level of user/kernel separation ?
I guess it can go in; it's forward progress, even if it doesn't make the
improvements I would like to
On Tue, Apr 16, 2019 at 11:36:18AM -0700, Ruslan Babayev wrote:
> Provide support for Infineon Dual Output Digital Multi-Phase Buck
> Controllers IR35215 and IR3570B.
>
> Cc: xe-linux-exter...@cisco.com
> Signed-off-by: Ruslan Babayev
> ---
> Documentation/hwmon/ir35215 | 98
On Tue, Apr 16, 2019 at 12:41:31PM -0700, Nicolin Chen wrote:
> The CONFIG register has a 3-bit averaging mode field for users
> to setup the number of samples that are collected and averaged
> together. This is very useful to filter noise from sensor data.
>
> This patch adds a 'samples' sysfs
On Tue, Apr 16, 2019 at 11:36:16AM -0700, Ruslan Babayev wrote:
> Registers VOUT_COMMAND, VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW are
> described in PMBUS Spec Part II Rev 1.2. Exposing them in the PMBUS
> core allows the drivers to turn them on with a corresponding
> PMBUS_HAVE_VOUT_... flags.
>
>
The CONFIG register has a 3-bit averaging mode field for users
to setup the number of samples that are collected and averaged
together. This is very useful to filter noise from sensor data.
This patch adds a 'samples' sysfs node using hwmon_chip_samples
of hwmon core, and updates wait time
On Tue, Apr 16, 2019 at 11:36:17AM -0700, Ruslan Babayev wrote:
> On some devices (like IR35215) READ_VIN and READ_IIN registers are
> paged.
>
> For devices where these registers are not paged the extra check
> ensures we expose only the registers that are actually present.
>
> Cc:
From: Ruslan Babayev
Registers VOUT_COMMAND, VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW are
described in PMBUS Spec Part II Rev 1.2. Exposing them in the PMBUS
core allows the drivers to turn them on with a corresponding
PMBUS_HAVE_VOUT_... flags.
Cc: xe-linux-exter...@cisco.com
Signed-off-by: Ruslan
From: Ruslan Babayev
On some devices (like IR35215) READ_VIN and READ_IIN registers are
paged.
For devices where these registers are not paged the extra check
ensures we expose only the registers that are actually present.
Cc: xe-linux-exter...@cisco.com
Signed-off-by: Ruslan Babayev
---
From: Ruslan Babayev
Provide support for Infineon Dual Output Digital Multi-Phase Buck
Controllers IR35215 and IR3570B.
Cc: xe-linux-exter...@cisco.com
Signed-off-by: Ruslan Babayev
---
Documentation/hwmon/ir35215 | 98 +++
drivers/hwmon/pmbus/Kconfig | 10
From: Ruslan Babayev
TPS40422 has MFR_SPECIFIC registers STEP_VREF_MARGIN_HIGH and
STEP_VREF_MARGIN_LOW, which are signed 16-bit in units of 2mV. This
value is an offset from the nominal reference voltage of 600mV.
For instance, the default value of STEP_VREF_MARGIN_LOW is -30
(decimal), which
TPS40422 has MFR_SPECIFIC registers STEP_VREF_MARGIN_HIGH and
STEP_VREF_MARGIN_LOW, which are signed 16-bit in units of 2mV. This
value is an offset from the nominal reference voltage of 600mV.
For instance, the default value of STEP_VREF_MARGIN_LOW is -30
(decimal), which corresponds to a
Provide support for Infineon Dual Output Digital Multi-Phase Buck
Controllers IR35215 and IR3570B.
Cc: xe-linux-exter...@cisco.com
Signed-off-by: Ruslan Babayev
---
Documentation/hwmon/ir35215 | 98 +++
drivers/hwmon/pmbus/Kconfig | 10
Registers VOUT_COMMAND, VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW are
described in PMBUS Spec Part II Rev 1.2. Exposing them in the PMBUS
core allows the drivers to turn them on with a corresponding
PMBUS_HAVE_VOUT_... flags.
Cc: xe-linux-exter...@cisco.com
Signed-off-by: Ruslan Babayev
---
The help text needs to spell out how the driver runs on a BMC, as it
previously seemed to indicate it ran on a POWER processor.
Signed-off-by: Eddie James
---
Changes since v1: fix Signed-off-by; git config got mixed up.
drivers/hwmon/occ/Kconfig | 12
1 file changed, 8
The error sysfs attribute returns the stored error state of the OCC and
doesn't depend on the OCC poll response. Therefore, split the error
attribute into it's own function to avoid failing out of the function if
the poll response fails.
Signed-off-by: Eddie James
---
drivers/hwmon/occ/sysfs.c
The OCC driver limits the rate of sending poll commands to the OCC. If a
user reads a hwmon entry after a poll response resulted in an error and
is rate-limited, the error is invisible to the user. Fix this by storing
the last error and returning that in the rate-limited case.
Signed-off-by:
This patch set adds BIOS Post code (BPC) support for the
Nuvoton NPCM Baseboard Management Controller (BMC).
Nuvoton BMC NPCM BIOS Post Code (BPC) monitoring two
configurable I/O addresses written by the host on the
Low Pin Count (LPC) bus, the capture data stored in 128-word FIFO.
NPCM BPC can
Add Nuvoton BMC NPCM BIOS post code (BPC) driver.
The NPCM BPC monitoring two I/O address written by
the host on the Low Pin Count (LPC) bus, the capure
data stored in 128-word FIFO.
Signed-off-by: Tomer Maimon
---
drivers/misc/Kconfig | 8 +
drivers/misc/Makefile |
Added device tree binding documentation for Nuvoton BMC
NPCM BIOS Post Code (BPC) and Apeed AST2500 LPC snoop.
The LPC snoop monitoring two configurable I/O addresses
written by the host on Low Pin Count (LPC) bus.
Signed-off-by: Tomer Maimon
Reviewed-by: Andrew Jeffery
---
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