On Tue, 2019-10-08 at 13:11 -0700, Guenter Roeck wrote:
>
> On Tue, Oct 08, 2019 at 03:59:49PM +, Sa, Nuno wrote:
> [ ... ]
> > > > +
> > > > + ctl->irq = platform_get_irq(pdev, 0);
> > > > + if (ctl->irq < 0) {
> > >
> > > This can return -EPROBE_DEFER. On top of that, it already
On Tue, Oct 08, 2019 at 03:59:49PM +, Sa, Nuno wrote:
[ ... ]
> > > +
> > > + ctl->irq = platform_get_irq(pdev, 0);
> > > + if (ctl->irq < 0) {
> >
> > This can return -EPROBE_DEFER. On top of that, it already generates
> > an error
> > message, meaning another one here is unnecessary.
>
> Wh
Hi Guenter,
One question/doubt that I just noticed now...
On Sun, 2019-10-06 at 08:32 -0700, Guenter Roeck wrote:
>
> On Thu, Sep 26, 2019 at 12:39:24PM +0200, Nuno Sá wrote:
> > The purpose of this IP Core is to control the fan used for the
> > cooling of a
> > Xilinx Zynq Ultrascale+ MPSoC wit
On Mon, 2019-10-07 at 07:18 -0700, Guenter Roeck wrote:
>
> On 10/7/19 6:52 AM, Sa, Nuno wrote:
> [ ... ]
> > > > +static long axi_fan_control_get_pwm_duty(const struct
> > > > axi_fan_control_data *ctl)
> > > > +{
> > > > + u32 pwm_width =
> > > > axi_fan_control_ioread(ADI_REG_PWM_WIDTH,
On 10/7/19 6:52 AM, Sa, Nuno wrote:
[ ... ]
+static long axi_fan_control_get_pwm_duty(const struct
axi_fan_control_data *ctl)
+{
+ u32 pwm_width = axi_fan_control_ioread(ADI_REG_PWM_WIDTH, ctl);
+ u32 pwm_period = axi_fan_control_ioread(ADI_REG_PWM_PERIOD,
ctl);
+
+ return DIV_R
On Sun, 2019-10-06 at 08:32 -0700, Guenter Roeck wrote:
>
> On Thu, Sep 26, 2019 at 12:39:24PM +0200, Nuno Sá wrote:
> > The purpose of this IP Core is to control the fan used for the
> > cooling of a
> > Xilinx Zynq Ultrascale+ MPSoC without the need of any external
> > temperature
> > sensors. T
On Thu, Sep 26, 2019 at 12:39:24PM +0200, Nuno Sá wrote:
> The purpose of this IP Core is to control the fan used for the cooling of a
> Xilinx Zynq Ultrascale+ MPSoC without the need of any external temperature
> sensors. To achieve this, the IP core uses the PL SYSMONE4 primitive to
> obtain the
The purpose of this IP Core is to control the fan used for the cooling of a
Xilinx Zynq Ultrascale+ MPSoC without the need of any external temperature
sensors. To achieve this, the IP core uses the PL SYSMONE4 primitive to
obtain the PL temperature and, based on those readings, it then outputs
a PW
