From: Po-Yu Chuang ratb...@faraday-tech.com
Support for Faraday FTIIC010 I2C controller. It is used on
Faraday A320, A369 and some other ARM SoC's.
Signed-off-by: Po-Yu Chuang ratb...@faraday-tech.com
---
drivers/i2c/busses/Kconfig|7 +
drivers/i2c/busses/Makefile |1 +
hi, Jean:
here is the structur of i2c_msg,
struct i2c_msg {
__u16 addr; /* slave address */
__u16 flags;
#define I2C_M_TEN 0x0010 /* this is a ten bit chip address */
#define I2C_M_RD 0x0001 /* read data, from
The original algorithm doesn't perform very well in some cases, e.g.
When the source clock of the I2C controller is 66MHz, and the
requested rate is 100KHz, it gives a divider of 768 instead of
the better 640.
Choose a better clock divider so the final clock rate is closer to
the requested
On OMAP4 OMAP_I2C_STAT_NACK is causing a timeout on the next access.
The isr cleans all flags in OMAP_I2C_CON_REG by setting OMAP_I2C_CON_STP
OMAP_I2C_CON_STP is also set in omap_i2c_xfer_msg on the last message.
According to the TI TSR the sequence for OMAP_I2C_STAT_NACK and
OMAP_I2C_STAT_AL are
Hi, I have hit upon a bug in this driver in the 2.6.32 which caused
memory corrupt and crash in my kernel. It appears to be still present
in 3.0-rc3 so as you are listed as the current kernel i2c maintainers
which covers i2c-ocores I thought you could comment on it and the
proposed fix I enclose
