From: David Wu
The i2c controller of new version1 supports highspeed mode,
1.7M and 3.4M rate. It also could be calculated divs by the rules.
The final divs would be effected a lot by hardware elements like
scl_rise_ns, scl_fall_ns and sda_rise_ns,sds_fall_ns.
Signed-off-by: David Wu
From: David Wu
There was an issue about "repeated start" timing at the I2C controller
of old version:
- controller appears to drop SDA at .875x (7/8) programmed clk high.
- controller appears to keep SCL high for 2x programmed clk high.
The first rule isn't enough
The calc_divs of new version is different form the old.
The time of tHD;sda, tHD;sda, tSU;sta, tHD;sta and tSU;sto
could be configured by RKI2C_CON register.
So it need a new way to calc_divs for new i2c controller.
Signed-off-by: David Wu
Signed-off-by: David Wu
---
drivers/i2c/busses/i2c
1. support highspeed.
2. check i2c bus idle status.
Change-Id: I9c22e752af621c0f8dbcbd399c86b34fd810ec38
Signed-off-by: David Wu
---
drivers/i2c/busses/i2c-rk3x.c | 336 --
1 file changed, 320 insertions(+), 16 deletions(-)
mode change 100644 => 100