On Mon, 2 May 2011 10:27:34 +0100, Ben Dooks wrote:
On Thu, Apr 28, 2011 at 11:15:44PM +0800, Haojian Zhuang wrote:
Both AP and CP are contained in Marvell PXA910 silicon. These two ARM
cores are sharing one pair of I2C pins.
In order to keep I2C transaction operated with atomic,
On Thu, Apr 28, 2011 at 4:22 PM, Jean Delvare kh...@linux-fr.org wrote:
Hi Haojian,
On Thu, 28 Apr 2011 12:02:36 +0800, Haojian Zhuang wrote:
Both AP and CP are contained in Marvell PXA910 silicon. These two ARM
cores are sharing one pair of I2C pins.
In order to keep I2C transaction
Hi Eric,
On Thu, 28 Apr 2011 16:36:02 +0800, Eric Miao wrote:
On Thu, Apr 28, 2011 at 4:22 PM, Jean Delvare kh...@linux-fr.org wrote:
Hi Haojian,
On Thu, 28 Apr 2011 12:02:36 +0800, Haojian Zhuang wrote:
Both AP and CP are contained in Marvell PXA910 silicon. These two ARM
cores are
On Thu, Apr 28, 2011 at 10:37 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Thu, Apr 28, 2011 at 04:16:25PM +0200, Jean Delvare wrote:
Are you suggesting that the hardware lock wouldn't mind being taken
twice by the AP side? If it is the case, then indeed the software mutex
is
Both AP and CP are contained in Marvell PXA910 silicon. These two ARM
cores are sharing one pair of I2C pins.
In order to keep I2C transaction operated with atomic, hardware lock
(RIPC) is required. Because of this, bus lock in AP side can't afford
this requirement. Now hardware lock is appended.
Both AP and CP are contained in Marvell PXA910 silicon. These two ARM
cores are sharing one pair of I2C pins.
In order to keep I2C transaction operated with atomic, hardware lock
(RIPC) is required. Because of this, bus lock in AP side can't afford
this requirement. Now hardware lock is appended.
